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27 条记录 (耗时 0.047 秒)

    Technique for subwoofer distance measurement
    12.
    发明申请
    Technique for subwoofer distance measurement 有权
    低音炮距离测量技术

    公开(公告)号：US20060062397A1

    公开(公告)日：2006-03-23

    申请号：US11002102

    申请日：2004-12-03

    申请人： Joel Cooper

    发明人： Joel Cooper

    IPC分类号： H04R29/00 ,  G01C25/00 ,  G06F19/00

    CPC分类号： H04S7/301 ,  G01S11/14

    摘要： The present invention automatically corrects for subwoofer or other speaker crossover settings or other parameters by providing an adjustable factor passed upon not only pulse location, but on pulse width. In FIG. 2, as the low-pass frequency of the subwoofer is decreased, either by the crossover setting or the physical design of the subwoofer, the impulse response is shifted to the right and the width of the impulse increases. By relating the adjustment factor to the width of the impulse, the accuracy of the computed distance is greatly increased. The relation may be found doing a simple polynomial curve fitting to empirical data from several subwoofers at various crossover settings and distances, storing that data, and then measuring pulse location and width of the actual subwoofer during the setup routine, and adjusting the distance (delay) calculations accordingly.

    摘要翻译： 本发明通过提供不仅脉冲位置传递的可调节因数而且脉冲宽度来自动校正重低音扬声器或其他扬声器交叉设置或其他参数。 在图 如图2所示，由于低音炮的低通频率通过交叉设置或超低音扬声器的物理设计降低，脉冲响应向右移动，脉冲宽度增加。 通过将调整因子与脉冲宽度相关联，计算出的距离的精度大大增加。 可以找到这样的关系：在各种交叉设置和距离处，从几个低音炮的经验数据拟合简单的多项式曲线，存储该数据，然后在设置程序期间测量实际重低音扬声器的脉冲位置和宽度，并调整距离（延迟 ）相应计算。

    Remote cathodic protection monitoring system
    13.
    发明授权
    Remote cathodic protection monitoring system 失效
    远程阴极保护监控系统

    公开(公告)号：US5999107A

    公开(公告)日：1999-12-07

    申请号：US967963

    申请日：1997-11-12

    申请人： Joel Cooper ,  Albert W. Gershman ,  Joe W. McCarty ,  Arthur Shapiro ,  Christopher J. Ziolkowski

    发明人： Joel Cooper ,  Albert W. Gershman ,  Joe W. McCarty ,  Arthur Shapiro ,  Christopher J. Ziolkowski

    IPC分类号： C23F13/00 ,  C23F13/22 ,  G08B21/00

    CPC分类号： C23F13/22

    摘要： A cathodic protection monitoring system for buried metal objects comprising a transponder hard-wire connected to a sacrificial anode and a reference electrode, each of the transponder, the sacrificial anode and the reference electrode being buried underground in close proximity to the buried metal object to be protected, thereby forming a first principal circuit between the sacrificial anode and the buried metal object and forming a second principal circuit between the reference electrode and the buried metal object. The system further comprises a portable transceiver disposed above ground tuned to a frequency of the transponder. Power for operation of the transponder is drawn from the cathodic protection circuit, thereby obviating the need for connections to above ground power supplies.

    摘要翻译： 一种用于掩埋金属物体的阴极保护监测系统，包括连接到牺牲阳极和参考电极的应答器硬线，应答器，牺牲阳极和参考电极中的每一个被埋在地下，靠近埋藏的金属物体 从而在牺牲阳极和掩埋金属物体之间形成第一主电路，并在参考电极和埋入的金属物体之间形成第二主电路。 该系统还包括设置在地面上的便携式收发器，调谐到应答器的频率。 从阴极保护电路抽出应答器的工作电源，从而避免了连接到地面电源的需要。

    Method and system for proximity-aware circuit design
    14.
    发明授权
    Method and system for proximity-aware circuit design 有权
    接近感知电路设计方法与系统

    公开(公告)号：US08281270B2

    公开(公告)日：2012-10-02

    申请号：US12870559

    申请日：2010-08-27

    申请人： Patrick G. Drennan ,  Ryan Silk ,  Joel Cooper ,  Jeffrey Dyck ,  Samer Sallam ,  Trent Lome McConaghy

    发明人： Patrick G. Drennan ,  Ryan Silk ,  Joel Cooper ,  Jeffrey Dyck ,  Samer Sallam ,  Trent Lome McConaghy

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.

    摘要翻译： 一种用于接近感知电路设计的方法，其中根据布局效应模型确定满足预定性能或产量目标的一组布局约束值。 然后选择布局约束值中的一个作为布局设计的约束输入，并且利用所选择的布局约束值执行设计布局，以为半导体电路提供半导体电路设计。 可以通过改变布局效应模型的实例参数来确定一组布局约束值，以根据布局效应模型来确定满足至少一个预定表现或收益目标的一组实例参数，并且确定相关联的布局约束 与实例参数集合的每个实例参数，从而在可以根据性能和/或产出权衡来评估的设计空间中提供多个候选。

    Global statistical optimization, characterization, and design
    15.
    发明授权
    Global statistical optimization, characterization, and design 有权
    全局统计优化，表征和设计

    公开(公告)号：US08024682B2

    公开(公告)日：2011-09-20

    申请号：US12396972

    申请日：2009-03-03

    申请人： Trent Lorne McConaghy ,  Pat Drennan ,  Joel Cooper ,  Jeffrey Dyck ,  David Callele ,  Shawn Rusaw ,  Samer Sallam ,  Jiangdon Ge ,  Anthony Arkles ,  Kristopher Breen ,  Sean Cocks

    发明人： Trent Lorne McConaghy ,  Pat Drennan ,  Joel Cooper ,  Jeffrey Dyck ,  David Callele ,  Shawn Rusaw ,  Samer Sallam ,  Jiangdon Ge ,  Anthony Arkles ,  Kristopher Breen ,  Sean Cocks

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063

    摘要： For application to analog, mixed-signal, and custom digital circuits, a system and method to do: global statistical optimization (GSO), global statistical characterization (GSC), global statistical design (GSD), and block-specific design. GSO can perform global yield optimization on hundreds of variables, with no simplifying assumptions. GSC can capture and display mappings from design variables to performance, across the whole design space. GSC can handle hundreds of design variables in a reasonable time frame, e.g., in less than a day, for a reasonable number of simulations, e.g., less than 100,000. GSC can capture design variable interactions and other possible nonlinearities, explicitly capture uncertainties, and intuitively display them. GSD can support the user's exploration of design-to-performance mappings with fast feedback, thoroughly capturing design variable interactions in the whole space, and allow for more efficiently created, more optimal designs. Block-specific design should make it simple to design small circuit blocks, in less time and with lower overhead than optimization through optimization.

    摘要翻译： 对于应用于模拟，混合信号和定制数字电路的系统和方法：全局统计优化（GSO），全局统计特征（GSC），全局统计设计（GSD）和块特定设计。 GSO可以对数百个变量执行全局收益优化，而不需要简化假设。 GSC可以在整个设计空间中捕获并显示从设计变量到性能的映射。 GSC可以在合理的时间范围内处理数百个设计变量，例如在不到一天的时间内，对于合理数量的模拟，例如小于100,000。 GSC可以捕获设计变量交互和其他可能的非线性，明确地捕获不确定性，并直观显示它们。 GSD可以通过快速反馈支持用户对设计到性能映射的探索，彻底地捕获整个空间中的设计变量交互，并允许更有效地创建，更优化的设计。 块特定设计应使设计小电路块的设计变得简单，在优化过程中，在更短的时间内和更低的开销。

    METHOD AND SYSTEM FOR IDENTIFYING RARE-EVENT FAILURE RATES
    18.
    发明申请
    METHOD AND SYSTEM FOR IDENTIFYING RARE-EVENT FAILURE RATES 有权
    识别突发事件失败率的方法和系统

    公开(公告)号：US20130226544A1

    公开(公告)日：2013-08-29

    申请号：US13881866

    申请日：2011-10-27

    申请人： Trent Lorne Mcconaghy ,  Joel Cooper ,  Jeffrey Dyvk ,  Kyle Fisher

    发明人： Trent Lorne Mcconaghy ,  Joel Cooper ,  Jeffrey Dyvk ,  Kyle Fisher

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036 ,  G06F2217/10

    摘要： A method and system to estimate failure rates in designs. N Monte Carlo samples are drawn from the random distribution that describes process variation in the design. A subset of these samples is selected, and that subset of Ninit samples are simulated (with a circuit simulator) to measure a performance value for each sample. A model is constructed, using the values of the Ninit process points as training inputs, and the corresponding Ninit performance values as training outputs. The candidate Monte Carlo samples are from the N Monte Carlo samples that have not yet been simulated. Each candidate is simulated on the model to get predicted performance values, and the samples are ordered in ascending (or descending) order of the predicted performance values. Simulation of candidates samples is then begun, in that order. The sampling and simulation will stops once there is sufficient confidence that all failures are found.

    摘要翻译： 一种估计设计失败率的方法和系统。 N蒙特卡洛样本是从设计中描述过程变化的随机分布中得出的。 选择这些样本的子集，并且模拟Ninit样本的子集（使用电路模拟器）来测量每个样本的性能值。 使用Ninit过程点的值作为训练输入，并将相应的Ninit性能值作为训练输出构建一个模型。 候选蒙特卡洛样本来自尚未模拟的N蒙特卡罗样本。 在模型上模拟每个候选人以获得预测的性能值，并且以预测的性能值的升序（或降序）顺序排列样本。 然后按照顺序开始模拟候选样本。 一旦有足够的信心发现所有故障，采样和仿真将停止。

    Pruning-based variation-aware design
    19.
    发明授权
    Pruning-based variation-aware design 有权
    基于修剪的变异感知设计

    公开(公告)号：US08074189B2

    公开(公告)日：2011-12-06

    申请号：US12366239

    申请日：2009-02-05

    申请人： Trent Lorne McConaghy ,  Jeffrey Dyck ,  Samer Sallam ,  Kristopher Breen ,  Joel Cooper ,  Jiandong Ge

    发明人： Trent Lorne McConaghy ,  Jeffrey Dyck ,  Samer Sallam ,  Kristopher Breen ,  Joel Cooper ,  Jiandong Ge

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F2217/10

    摘要： For application to analog, mixed-signal, and custom digital circuits, a system and method to begin with a complex problem description that encompasses many variables from statistical manufacturing, the circuit's environment, and the circuit's design parameters, but then apply techniques to prune the scope of the problem to make it manageable for manual design and more efficient automated design, and finally use that pruned problem for more efficient and effective design.

    摘要翻译： 对于应用于模拟，混合信号和定制数字电路的系统和方法，从复杂的问题描述开始，包括统计制造，电路环境和电路设计参数中的许多变量，然后应用技术来修剪 问题的范围使其易于手动设计和更有效的自动化设计，最后使用修剪的问题来更有效和有效的设计。

    PROXIMITY-AWARE CIRCUIT DESIGN METHOD
    20.
    发明申请
    PROXIMITY-AWARE CIRCUIT DESIGN METHOD 有权
    临近电路设计方法

    公开(公告)号：US20110055782A1

    公开(公告)日：2011-03-03

    申请号：US12870559

    申请日：2010-08-27

    申请人： Patrick G. DRENNAN ,  Ryan Silk ,  Joel Cooper ,  Jeffrey Dyck ,  Samer Sallam ,  Trent Lorne McCONAGHY

    发明人： Patrick G. DRENNAN ,  Ryan Silk ,  Joel Cooper ,  Jeffrey Dyck ,  Samer Sallam ,  Trent Lorne McCONAGHY

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.

    摘要翻译： 一种用于接近感知电路设计的方法，其中根据布局效应模型确定满足预定性能或产量目标的一组布局约束值。 然后选择布局约束值中的一个作为布局设计的约束输入，并且利用所选择的布局约束值执行设计布局，以为半导体电路提供半导体电路设计。 可以通过改变布局效应模型的实例参数来确定一组布局约束值，以根据布局效应模型来确定满足至少一个预定表现或收益目标的一组实例参数，并且确定相关联的布局约束 与实例参数集合的每个实例参数，从而在可以根据性能和/或产出权衡来评估的设计空间中提供多个候选。