公开(公告)号：US08045400B2

公开(公告)日：2011-10-25

申请号：US12495269

申请日：2009-06-30

Applicant: Je-Yoon Kim ,  Jong-Chern Lee

Inventor： Je-Yoon Kim ,  Jong-Chern Lee

IPC: G11C7/00

CPC classification number: G11C19/00

Abstract: A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.

Abstract translation: 用于控制读周期的电路包括被配置为依次移位读信号的多个移位级; 以及激活单元，被配置为通过对所述多个移位级的输出信号执行逻辑运算来激活表示读取周期的读取周期信号，其中所述多个移位级被配置为将所读取的信号顺序地移位一段时间 对应于突发设置信息。

公开(公告)号：US20080001582A1

公开(公告)日：2008-01-03

申请号：US11717662

申请日：2007-03-14

Applicant: Jong-Chern Lee ,  Sun-Hye Shin

Inventor： Jong-Chern Lee ,  Sun-Hye Shin

IPC: G05F1/10

CPC classification number: G05F1/465

Abstract: An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.

Abstract translation: 半导体存储器件的内部电压发生器能够改变待机模式和有源模式之间的驱动能力，以便在待机模式下更快地响应并防止在待机模式下的漏电流。 半导体存储器件的内部电压发生器包括用于产生具有关于待机和有功模式的信息的驱动控制信号的驱动控制器，通过用于将内部电压与待机和有效模式下的参考电压进行比较的驱动控制信号使能的第一电压发生器 模式，用于根据由第一电压发生器进行的比较产生内部电压的第一驱动器，通过用于将内部电压与活动模式中的参考电压进行比较的驱动控制信号使能的第二电压发生器和用于 根据由第二电压发生器执行的比较产生内部电压。

公开(公告)号：US07157893B2

公开(公告)日：2007-01-02

申请号：US10878568

申请日：2004-06-29

Applicant: Jong-Chern Lee

Inventor： Jong-Chern Lee

IPC: G05F3/16

CPC classification number: G05F3/245 ,  Y10S323/907

Abstract: There is provided a reference voltage generator that generates a constant reference voltage regardless of a change in temperature. The reference voltage generator includes a temperature-compensated current generating part for reducing a supply current provided to an output terminal in response to an increase of temperature, and a diode for receiving the supply current through the output terminal.

Abstract translation: 提供了参考电压发生器，其产生恒定的参考电压，而与温度的变化无关。 参考电压发生器包括温度补偿电流产生部件，用于响应于温度升高而减小提供给输出端子的电源电流;以及二极管，用于接收通过输出端子的电源电流。

公开(公告)号：US08446197B2

公开(公告)日：2013-05-21

申请号：US12755949

申请日：2010-04-07

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03L7/00

CPC classification number: H03L7/0814 ,  H03L7/07

Abstract: A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.

Abstract translation: 延迟锁定环包括延迟脉冲产生单元，编码单元和延迟线。 延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。 编码单元被配置为对延迟脉冲进行编码并输出代码值。 延迟线被配置为通过代码值来延迟输入时钟，并产生延迟的锁定时钟。 延迟脉冲在与第一周期（对应于输入时钟的整数倍）和第二周期（在某个复制延迟周期）之间的差值的第三周期内具有逻辑高电平状态。

公开(公告)号：US20120249229A1

公开(公告)日：2012-10-04

申请号：US13236970

申请日：2011-09-20

Applicant: Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

Inventor： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

IPC: H01L25/00

CPC classification number: G11C8/12

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

Abstract translation: 半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号 以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

公开(公告)号：US08242822B2

公开(公告)日：2012-08-14

申请号：US13400967

申请日：2012-02-21

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03L7/06

CPC classification number: H03L7/0816 ,  H03L7/0814

Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

公开(公告)号：US08233339B2

公开(公告)日：2012-07-31

申请号：US12875803

申请日：2010-09-03

Applicant: Hyun-Su Yoon ,  Jong-Chern Lee ,  Seung-Joon Ahn

Inventor： Hyun-Su Yoon ,  Jong-Chern Lee ,  Seung-Joon Ahn

IPC: G11C7/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C2207/2272

Abstract: A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.

Abstract translation: 半导体存储器件包括开环型延迟锁定环（DLL），其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号 等待时间控制单元，被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令，并输出移位的命令;以及附加延迟线，被配置为根据延迟代码值来延迟移位的命令 对应于第二延迟量，并且输出控制哪个操作定时的命令。

公开(公告)号：US20120051113A1

公开(公告)日：2012-03-01

申请号：US12945120

申请日：2010-11-12

Applicant: Min-Seok CHOI ,  Jong-Chern Lee

Inventor： Min-Seok CHOI ,  Jong-Chern Lee

IPC: G11C5/02 ,  G11C5/06 ,  H01L21/50

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C29/12 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a plurality of slave chips each including a core area including a memory cell array, a global data line configured to transfer input/output data of the corresponding core area, and a first peripheral circuit area configured to interface the corresponding core area and the corresponding global data line, a plurality of data transfer through-chip vias vertically formed through the plurality of slave chips, respectively, and coupled to the respective global data lines of the slave chips, and a master chip including a second peripheral circuit area configured to provide an input/output interface between the data transfer through-chip vias and an external controller.

Abstract translation: 半导体集成电路包括多个从芯片，每个从芯片包括包括存储单元阵列的核心区域，被配置为传送相应核心区域的输入/输出数据的全局数据线以及被配置为将对应的核心 区域和对应的全局数据线，分别通过多个从芯片垂直形成并耦合到从芯片的相应全局数据线的多个数据传输通过芯片通孔，以及包括第二外围电路的主芯片 区域被配置为在数据传送片上通孔和外部控制器之间提供输入/输出接口。

公开(公告)号：US20120049361A1

公开(公告)日：2012-03-01

申请号：US12980828

申请日：2010-12-29

Applicant: Byoung-Kwon PARK ,  Jong-Chern Lee

Inventor： Byoung-Kwon PARK ,  Jong-Chern Lee

IPC: H01L23/485 ,  H01L21/50

CPC classification number: H01L25/0657 ,  G11C5/025 ,  H01L23/147 ,  H01L23/50 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor integrated circuit includes a semiconductor chip including a memory cell array, a plurality of first through-chip vias configured to vertically penetrate through the semiconductor chip and operate as an interface for a signal and a supply voltage, and a semiconductor substrate. The semiconductor substrate includes a peripheral circuit region coupled to the plurality of first through-chip vias and configured to control the semiconductor chip and a conductivity pattern region configured to operate as an interface for the signal and the supply voltage between the peripheral circuit region and an external controller.

Abstract translation: 半导体集成电路包括：半导体芯片，包括存储单元阵列;多个第一贯通芯片通孔，其被配置为垂直穿过半导体芯片并作为信号和电源电压的接口进行操作;以及半导体衬底。 半导体衬底包括耦合到多个第一通孔的外围电路区域，并被配置为控制半导体芯片和导电图案区域，其被配置为作为信号的接口和外围电路区域与外部电路区域之间的电源电压 外部控制器

公开(公告)号：US20120007624A1

公开(公告)日：2012-01-12

申请号：US12914424

申请日：2010-10-28

Applicant: Sang-Jin Byeon ,  Jong-Chern Lee

Inventor： Sang-Jin Byeon ,  Jong-Chern Lee

IPC: G01R31/26

CPC classification number: G11C11/4072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C16/20

Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

Abstract translation: 用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。 第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。 通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据 比较结果。