公开(公告)号：US20070045671A1

公开(公告)日：2007-03-01

申请号：US11485485

申请日：2006-07-13

申请人： Sung-jun Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-kwang Choi

发明人： Sung-jun Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-kwang Choi

IPC分类号： H01L29/768

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/12

摘要： A multi-level transistor comprising a second active region having a single-crystalline characteristic and a method for manufacturing the multi-level transistor are disclosed. The multi-level transistor comprises a substrate comprising a first active region, a first transistor formed on the first active region, a first insulating layer covering the first transistor, and adapted to isolate the first active region, a second active region comprising a patterned first selective epitaxial growth (SEG) layer formed on the first insulating layer, and a second transistor formed on the second active region.

摘要翻译： 公开了一种包括具有单晶特性的第二有源区和多电平晶体管的制造方法的多电平晶体管。 所述多电平晶体管包括衬底，所述衬底包括第一有源区，形成在所述第一有源区上的第一晶体管，覆盖所述第一晶体管的第一绝缘层，并且适于隔离所述第一有源区;第二有源区， 形成在第一绝缘层上的选择性外延生长（SEG）层和形成在第二有源区上的第二晶体管。

公开(公告)号：US06626968B2

公开(公告)日：2003-09-30

申请号：US09861697

申请日：2001-05-21

申请人： Young-rae Park ,  Jung-yup Kim ,  Bo-un Yoon ,  Kwang-bok Kim ,  Jae-phil Boo ,  Jong-won Lee ,  Sang-rok Hah ,  Kyung-hyun Kim ,  Chang-ki Hong

发明人： Young-rae Park ,  Jung-yup Kim ,  Bo-un Yoon ,  Kwang-bok Kim ,  Jae-phil Boo ,  Jong-won Lee ,  Sang-rok Hah ,  Kyung-hyun Kim ,  Chang-ki Hong

IPC分类号： C09G102

CPC分类号： H01L21/76224 ,  B24B37/044 ,  C09G1/02 ,  H01L21/31053

摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

公开(公告)号：US20120028435A1

公开(公告)日：2012-02-02

申请号：US13240475

申请日：2011-09-22

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

公开(公告)号：US07535052B2

公开(公告)日：2009-05-19

申请号：US11763137

申请日：2007-06-14

申请人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

发明人： Byoung-ho Kwon ,  Chang-ki Hong ,  Bo-un Yoon ,  Jun-yong Kim

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate.

摘要翻译： 提供了一种制造使用该方法制造的非易失性存储器集成电路器件和非易失性存储器集成电路器件的方法。 器件隔离区域形成在衬底中以限定电池阵列区域和外围电路区域。 在单元阵列区域中形成多个第一和第二预叠层栅极结构，并且每个都具有堆叠下部结构，导电图案和第一牺牲层图案的结构。 结区域形成在单元阵列区域中。 间隔件形成在第一和第二预堆叠栅极结构的侧壁上。 形成填充第二预堆叠栅极结构之间的每个空间的第二牺牲层图案。 第一牺牲层图案从第一和第二预堆叠栅极结构中的每一个去除。 在第一和第二预堆叠栅极结构的每个空间中形成镶嵌金属层图案，从中去除第一牺牲层图案，从而完成第一和第二堆叠栅极结构。 去除第二牺牲层图案。 在第一层叠栅极结构的顶表面，第二堆叠栅结构的顶表面和侧壁以及衬底的顶表面上形成停止层。

公开(公告)号：US07524757B2

公开(公告)日：2009-04-28

申请号：US11485485

申请日：2006-07-13

申请人： Sung-jun Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-kwang Choi

发明人： Sung-jun Kim ,  Chang-ki Hong ,  Bo-un Yoon ,  Jae-kwang Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/12

摘要： A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.

摘要翻译： 一种在衬底上制造多电平晶体管的方法。 该方法包括在第一有源区上形成第一晶体管，在衬底上形成第一选择性外延生长（SEG）层，形成初步的第二SEG层和虚设层，其中初步的第二SEG层直接形成 所述第一SEG层和形成在所述基板的单元区域上的所述第一绝缘层的一部分，并且所述虚设层形成在所述基板的周边区域上。 该方法还包括使用虚设层作为停止层平坦化初步的第二SEG层以形成第二SEG层，从形成在第一绝缘层上的第二SEG层形成第二有源区，并在第二绝缘层上形成第二晶体管 活跃区域。

公开(公告)号：US20070293048A1

公开(公告)日：2007-12-20

申请号：US11812140

申请日：2007-06-15

申请人： Jon-won Lee ,  Chang-ki Hong ,  Bo-un Yoon

发明人： Jon-won Lee ,  Chang-ki Hong ,  Bo-un Yoon

IPC分类号： H01L21/461 ,  B24D3/02 ,  C09K3/14

CPC分类号： H01L21/7684 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  H01L21/3212

摘要： A polishing slurry, including an oxidizer, a corrosion inhibitor, and a polishing rate enhancer, wherein the polishing rate enhancer is a heterocyclic compound having at least one nitrogen in the ring, and the nitrogen is not directly bonded to a hydrogen atom which is mostly dissociated in the slurry.

摘要翻译： 一种抛光浆料，包括氧化剂，缓蚀剂和抛光速率增强剂，其中抛光速率增强剂是环中至少有一个氮的杂环化合物，并且氮不直接键合到主要是氢原子 在浆液中解离。

公开(公告)号：US07196010B2

公开(公告)日：2007-03-27

申请号：US10639541

申请日：2003-08-12

申请人： Young-rae Park ,  Jung-yup Kim ,  Bo-un Yoon ,  Kwang-bok Kim ,  Jae-phil Boo ,  Jong-won Lee ,  Sang-rok Hah ,  Kyung-hyun Kim ,  Chang-ki Hong

发明人： Young-rae Park ,  Jung-yup Kim ,  Bo-un Yoon ,  Kwang-bok Kim ,  Jae-phil Boo ,  Jong-won Lee ,  Sang-rok Hah ,  Kyung-hyun Kim ,  Chang-ki Hong

IPC分类号： H01L21/302

CPC分类号： H01L21/76224 ,  B24B37/044 ,  C09G1/02 ,  H01L21/31053

摘要： A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

公开(公告)号：US09035396B2

公开(公告)日：2015-05-19

申请号：US13240475

申请日：2011-09-22

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L27/14 ,  H01L29/76 ,  H01L21/3105 ,  H01L27/105 ,  H01L29/66

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

公开(公告)号：US08053845B2

公开(公告)日：2011-11-08

申请号：US12291211

申请日：2008-11-07

申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

IPC分类号： H01L21/70

CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

公开(公告)号：US07846801B2

公开(公告)日：2010-12-07

申请号：US11833050

申请日：2007-08-02

申请人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

发明人： Sung-jun Kim ,  Seong-kyu Yun ,  Chang-ki Hong ,  Bo-un Yoon ,  Jong-won Lee ,  Ho-young Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/7851

摘要： Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

摘要翻译： 公开了一种制造包括多栅极晶体管的半导体器件的方法。 制造半导体器件的方法包括提供具有多个沿第一方向延伸的活性图案的半导体器件，被隔离层隔开并被第一绝缘层覆盖; 通过在第一方向上蚀刻位于彼此相邻的有源图案之间的隔离层来形成第一凹槽; 用钝化层掩埋第一槽; 通过在与所述第一方向相交的第二方向上蚀刻位于所述有源图案之间的所述隔离层来形成暴露所述有源图案的两侧的至少一部分的第二凹槽; 去除第一凹槽中的钝化层; 以及形成填充所述第二凹槽的至少一部分并沿所述第二方向延伸的栅极线。