公开(公告)号：US07432558B1

公开(公告)日：2008-10-07

申请号：US10863392

申请日：2004-06-09

Applicant: Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a orientation. A first gate may be formed on the insulating layer proximate to the side surface of the fin.

Abstract translation: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 可以在绝缘层上形成翅片。 翅片可以包括侧表面和顶表面，并且侧表面可以具有<100>取向。 第一栅极可以形成在靠近鳍片的侧表面的绝缘层上。

公开(公告)号：US06960804B1

公开(公告)日：2005-11-01

申请号：US10633034

申请日：2003-10-10

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

IPC: H01L21/027 ,  H01L21/336 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/785 ,  H01L21/0276 ,  H01L29/42392 ,  H01L29/66795

Abstract: A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.

Abstract translation: 双半导体器件包括衬底，绝缘层，鳍和栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 翅片具有多个侧表面，顶表面和底表面。 栅极形成在绝缘层上并且围绕半导体器件的沟道区域中的鳍的顶表面，底表面和侧表面。 用门材料围绕翅片会导致总通道宽度增加和设备调整裕度更灵活。

公开(公告)号：US06921963B2

公开(公告)日：2005-07-26

申请号：US10830006

申请日：2004-04-23

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

Abstract: A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.

Abstract translation: 这里描述了窄通道FinFET，其具有窄的通道宽度。 可以在窄通道上形成保护层，保护层比窄通道宽。

公开(公告)号：US5985726A

公开(公告)日：1999-11-16

申请号：US187635

申请日：1998-11-06

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66492 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dummy or sacrificial gate structure. Dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with spacers The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法利用虚拟或牺牲栅极结构。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成源极和漏极扩展。 开口可以填充间隔物该工艺可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US07259425B2

公开(公告)日：2007-08-21

申请号：US10348911

申请日：2003-01-23

Applicant: Judy Xilin An ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.

Abstract translation: 三栅极金属氧化物半导体场效应晶体管（MOSFET）包括翅片结构，邻近翅片结构的第一侧形成的第一栅极，与第一侧相对的翅片结构的第二侧附近形成的第二栅极，以及 形成在鳍结构顶部的顶门。 MOSFET周围的栅极包括多个散热片，邻近其中一个翅片形成的第一侧壁栅极结构，邻近另一个鳍片形成的第二侧壁栅极结构，形成在一个或多个翅片上的顶部栅极结构，以及底部栅极 在一个或多个翅片下形成的结构。

公开(公告)号：US07148526B1

公开(公告)日：2006-12-12

申请号：US10348758

申请日：2003-01-23

Applicant: Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

Abstract translation: 双栅极锗金属氧化物半导体场效应晶体管（MOSFET）包括锗翅片，邻近锗翅片的第一侧形成的第一栅极和与第一侧相对的锗翅片第二侧附近形成的第二栅极 。 三栅极MOSFET包括锗翅片，与锗翅片的第一侧相邻形成的第一栅极，与第一侧相对的锗翅片的第二侧附近形成的第二栅极和形成在锗翅片顶部上的顶栅极 。 全栅极MOSFET包括锗翅片，邻近锗翅片的第一侧形成的第一侧壁栅极结构，邻近锗翅片的第二侧形成的第二侧壁栅极结构，以及形成在锗翅片上和周围的附近的栅极结构 锗鳍

公开(公告)号：US06853020B1

公开(公告)日：2005-02-08

申请号：US10290330

申请日：2002-11-08

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7856 ,  H01L29/78684 ,  Y10S257/90

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is located on one side of the fin. A portion of the first gate includes conductive material doped with an n-type dopant. The second gate is formed on the insulating layer and is located on the opposite side of the fin as the first gate. A portion of the second gate includes conductive material doped with a p-type dopant.

Abstract translation: 双栅半导体器件包括衬底，绝缘层，鳍和两个栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 第一栅极形成在绝缘层上并且位于鳍的一侧。 第一栅极的一部分包括掺杂有n型掺杂剂的导电材料。 第二栅极形成在绝缘层上，并且位于作为第一栅极的鳍片的相对侧上。 第二栅极的一部分包括掺杂有p型掺杂剂的导电材料。

公开(公告)号：US06803631B2

公开(公告)日：2004-10-12

申请号：US10349042

申请日：2003-01-23

Applicant: Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L2701

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

Abstract: A semiconductor structure includes a fin and a layer formed on the fin. The fin includes a first crystalline material having a rectangular cross section and a number of surfaces. The layer is formed on the surfaces and includes a second crystalline material. The first crystalline material has a different lattice constant than the second crystalline material to induce tensile strain within the first layer.

Abstract translation: 半导体结构包括翅片和形成在翅片上的层。 翅片包括具有矩形横截面和多个表面的第一结晶材料。 该层形成在表面上并且包括第二结晶材料。 第一结晶材料具有与第二结晶材料不同的晶格常数，以在第一层内引起拉伸应变。

公开(公告)号：US06765227B1

公开(公告)日：2004-07-20

申请号：US10116791

申请日：2002-04-04

Applicant: Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

Inventor： Bin Yu ,  William G. En ,  Judy Xilin An ,  Concetta E. Riccobene

IPC: H01L2906

CPC classification number: H01L29/66742 ,  H01L21/76256 ,  H01L29/1054 ,  H01L29/78687 ,  Y10S438/977

Abstract: A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.

Abstract translation: 绝缘体上半导体（SOI）晶片。 晶片包括硅衬底，设置在衬底上的掩埋氧化物（BOX）层和设置在盒层上的有源层。 有源层具有设置在硅 - 锗层上的上硅层。 硅 - 锗层设置在下硅层上。 硅 - 锗层的硅 - 锗是应变的硅 - 锗，并且是大约至大约400埃。

公开(公告)号：US06716686B1

公开(公告)日：2004-04-06

申请号：US10613997

申请日：2003-07-08

Applicant: Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Judy Xilin An ,  Bin Yu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.

Abstract translation: 用于形成一个或多个FinFET器件的方法包括在氧化物层中形成源极区域和漏极区域，其中氧化物层设置在衬底上，并且蚀刻源极区域和漏极区域之间的氧化物层以形成基团 的第一装置的氧化物壁和通道。 该方法还包括在第一器件的氧化物壁和通道上沉积连接器材料，形成用于第一器件的栅极掩模，从通道移除连接器材料，将沟道材料沉积在第一器件的通道中，形成栅极 在沟道上的第一器件的电介质，在第一器件的栅极电介质上沉积栅极材料，以及图案化和蚀刻栅极材料以形成用于第一器件的至少一个栅电极。