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22 条记录 (耗时 0.047 秒)

    Using thick spacer for bitline implant then remove
    11.
    发明授权
    Using thick spacer for bitline implant then remove 有权
    使用厚间隔物进行位线植入，然后移除

    公开(公告)号：US07888218B2

    公开(公告)日：2011-02-15

    申请号：US11724775

    申请日：2007-03-16

    申请人： Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

    发明人： Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end processing.

    摘要翻译： 本发明涉及一种在半导体衬底上形成双位存储器芯阵列的至少一部分的系统方法，该方法包括形成相邻的第一存储单元处理组件; 包括电荷捕获电介质，第一多晶硅层并且在其间限定第一位线开口，在电荷俘获电介质层上形成第一多晶硅层特征，在电荷俘获电介质和第一多晶硅层特征之上沉积第二间隔物材料层， 形成与电荷俘获电介质相邻的侧壁间隔物，并且第一多晶硅层的特征在于限定相邻存储器单元之间的第二位线开口，执行位线注入或凹坑注入，或两者进入位线开口以在衬底内建立掩埋位线 具有比第一位线开口的相应宽度窄的各自的位线宽度，去除侧壁间隔件，以及执行后端处理。

    Programming a memory device
    12.
    发明授权
    Programming a memory device 有权
    编程内存设备

    公开(公告)号：US07269067B2

    公开(公告)日：2007-09-11

    申请号：US11174560

    申请日：2005-07-06

    申请人： Shankar Sinha ,  Zhizheng Liu ,  Yi He

    发明人： Shankar Sinha ,  Zhizheng Liu ,  Yi He

    IPC分类号： G11C11/34

    CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a source region associated with the memory cell and/or applying a negative bias to a substrate region associated with the memory cell.

    摘要翻译： 一种对非易失性存储器件中的存储器单元进行编程的方法包括：将第一电压施加到与存储器单元相关联的控制栅极，并将第二电压施加到与存储器单元相关联的漏极区域。 该方法还包括向与存储器单元相关联的源极区域施加正偏压和/或将负偏压施加到与存储器单元相关联的衬底区域。

    Dielectric extension to mitigate short channel effects
    14.
    发明申请
    Dielectric extension to mitigate short channel effects 有权
    电介质延伸以减轻短路效应

    公开(公告)号：US20080157199A1

    公开(公告)日：2008-07-03

    申请号：US11724725

    申请日：2007-03-16

    申请人： Vidyut Gopal ,  Shankar Sinha ,  Jean Yee-Mei Yang ,  Phillip L. Jones

    发明人： Vidyut Gopal ,  Shankar Sinha ,  Jean Yee-Mei Yang ,  Phillip L. Jones

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28123 ,  H01L21/31144 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/6653

    摘要： In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

    摘要翻译： 在图案化晶体管时，允许一层栅极电介质材料保留在其上形成晶体管的半导体衬底上。 这种剩余的介电材料阻止掺杂剂注入到下面的衬底中，有效地延长晶体管的沟道区。 这减轻了诸如泄漏电流等不需要的短通道效应，从而通过建立以更可预测或以其它方式所需的方式执行的晶体管来减轻产量损失。

    Using thick spacer for bitline implant then remove
    15.
    发明申请
    Using thick spacer for bitline implant then remove 有权
    使用厚间隔物进行位线植入，然后移除

    公开(公告)号：US20080153223A1

    公开(公告)日：2008-06-26

    申请号：US11724775

    申请日：2007-03-16

    申请人： Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

    发明人： Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end processing.

    摘要翻译： 本发明涉及一种在半导体衬底上形成双位存储器芯阵列的至少一部分的系统方法，该方法包括形成相邻的第一存储单元处理组件; 包括电荷捕获电介质，第一多晶硅层并且在其间限定第一位线开口，在电荷俘获电介质层上形成第一多晶硅层特征，在电荷俘获电介质和第一多晶硅层特征之上沉积第二间隔物材料层， 形成与电荷俘获电介质相邻的侧壁间隔物，并且第一多晶硅层的特征在于限定相邻存储器单元之间的第二位线开口，执行位线注入或凹坑注入，或两者进入位线开口以在衬底内建立掩埋位线 具有比第一位线开口的相应宽度窄的各自的位线宽度，去除侧壁间隔件，以及执行后端处理。

    Barrier region underlying source/drain regions for dual-bit memory devices
    17.
    发明授权
    Barrier region underlying source/drain regions for dual-bit memory devices 有权
    用于双位存储器件的源极/漏极区域的屏障区域

    公开(公告)号：US09171936B2

    公开(公告)日：2015-10-27

    申请号：US11634777

    申请日：2006-12-06

    申请人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    发明人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    IPC分类号： H01L29/66 ,  H01L21/265 ,  H01L27/115 ,  H01L29/792

    CPC分类号： H01L29/66833 ,  H01L21/26506 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792

    摘要： One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

    摘要翻译： 本发明的一个实施例涉及一种存储单元。 存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。 存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。 阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。 还公开了其他实施例。

    Memory cell dual pocket implant
    18.
    发明授权
    Memory cell dual pocket implant 有权
    记忆体双口袋植入

    公开(公告)号：US07678674B1

    公开(公告)日：2010-03-16

    申请号：US11211509

    申请日：2005-08-26

    申请人： Shankar Sinha ,  Ashot Melik-Martirosian ,  Ihsan Djomehri

    发明人： Shankar Sinha ,  Ashot Melik-Martirosian ,  Ihsan Djomehri

    IPC分类号： H01L21/425

    CPC分类号： H01L21/26586 ,  H01L27/11568 ,  H01L29/1083 ,  H01L29/792

    摘要： A method of forming implants for a memory cell includes forming an oxide-nitride-oxide (ONO) stack over a substrate and implanting first impurities in the substrate adjacent each side of the ONO stack using a first implantation energy and a first tilt angle to produce first pocket implants. The method further includes implanting second impurities in the substrate adjacent each side of the ONO stack using a second implantation energy and a second tilt angle to produce second pocket implants, where the second implantation energy is substantially larger than the first implantation energy and where the second tilt angle is substantially larger than the first tilt angle.

    摘要翻译： 用于形成存储器单元的种植体的方法包括在衬底上形成氧化物 - 氧化物 - 氧化物（ONO）堆叠，并且使用第一注入能量和第一倾斜角度在邻近ONO堆叠的每一侧的基板中注入第一杂质，以产生 第一口袋种植体。 该方法还包括使用第二注入能量和第二倾斜角度在邻近ONO堆叠的每一侧的衬底中注入第二杂质以产生第二袋植入物，其中第二注入能量基本上大于第一注入能量，其中第二种植入能量 倾斜角大致大于第一倾斜角。

    Barrier region for memory devices
    20.
    发明申请
    Barrier region for memory devices 有权
    存储设备的屏障区域

    公开(公告)号：US20080135902A1

    公开(公告)日：2008-06-12

    申请号：US11634777

    申请日：2006-12-06

    申请人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    发明人： Shankar Sinha ,  Yi He ,  Zhizheng Liu ,  Ming-Sang Kwan

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L29/66833 ,  H01L21/26506 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/792

    摘要： One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

    摘要翻译： 本发明的一个实施例涉及一种存储单元。 存储单元包括衬底和布置在衬底上的层叠栅极结构，其中堆叠栅极结构包括适于存储至少一位数据的电荷捕获介电层。 存储单元还包括衬底中的源极和漏极，其中源极和漏极设置在堆叠的栅极结构的相对侧。 阻挡区域基本上设置在源极或漏极下方并且包括惰性物质。 还公开了其他实施例。