公开(公告)号：US20220093615A1

公开(公告)日：2022-03-24

申请号：US17194591

申请日：2021-03-08

Applicant: Kioxia Corporation

Inventor： Harumi SEKI ,  Masumi SAITOH

IPC: H01L27/1159 ,  H01L27/11587 ,  H01L27/11597

Abstract: A semiconductor memory device of an embodiment includes a first gate electrode layer and a second gate electrode layer extending parallel to each other, a semiconductor layer between the first and the second gate electrode layer intersecting with the first and the second gate electrodes, and a dielectric layer surrounding the semiconductor layer, the dielectric layer containing oxygen and one of hafnium oxide or zirconium, the dielectric layer including a first region containing crystal of orthorhombic or trigonal as a main component between the first gate electrode layer and the semiconductor layer, a second region containing crystal of orthorhombic or trigonal as a main component between the second gate electrode layer and the semiconductor layer, and a third region containing a substance other than crystal of orthorhombic or trigonal as a main component between the first region and the second region.

公开(公告)号：US20220093152A1

公开(公告)日：2022-03-24

申请号：US17201114

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Reika TANAKA ,  Masumi SAITOH ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Hidehiro SHIGA

IPC: G11C11/22 ,  H01L27/11597

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

公开(公告)号：US20210089240A1

公开(公告)日：2021-03-25

申请号：US16803883

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Reika TANAKA ,  Takayuki MIYAZAKI ,  Masumi SAITOH

IPC: G06F3/06

Abstract: A storage device includes a substrate, first wirings arranged in a first direction and extending in a second direction, second wirings arranged in the second direction and extending in the first direction, resistance portions between the first and second wirings, third wirings between the second wirings and the substrate, arranged in the second direction and extending in a third direction, semiconductor portions each connected to second and third wirings, a fourth wiring extending in the second direction and facing the semiconductor portions, insulating portions between the semiconductor portions and the fourth wiring, and a contact connected to each first wiring. The semiconductor portions include a first portion and a second portion closer to the contact, and a length in the second direction of an insulating portion between the first portion and the fourth wiring is greater than that of another insulating portion between the second portion and the fourth wiring.

公开(公告)号：US20220301643A1

公开(公告)日：2022-09-22

申请号：US17459441

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Reiko SUMI ,  Reika TANAKA ,  Masumi SAITOH

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

公开(公告)号：US20220093149A1

公开(公告)日：2022-03-24

申请号：US17189097

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Haruka SAKUMA ,  Kiwamu SAKUMA ,  Masumi SAITOH

IPC: G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/51

Abstract: A semiconductor storage device includes a plurality of gate electrodes, a semiconductor layer facing the plurality of gate electrodes, a gate insulating layer arranged between each of the plurality of gate electrodes and the semiconductor layer. The gate insulating layer contains oxygen (O) and hafnium (Hf) and has an orthorhombic crystal structure. A plurality of first wirings is connected to the respective gate electrodes. A controller is configured to execute a write sequence and an erasing sequence by applying certain voltages to at least one of the first wirings. The controller is further configured to increase either a program voltage to be applied to the first wirings in the write sequence or an application time of the program voltage in the write sequence after a total number of executions of the write sequence or the erasing sequence has reached a particular number.

公开(公告)号：US20210278437A1

公开(公告)日：2021-09-09

申请号：US17008803

申请日：2020-09-01

Applicant: Kioxia Corporation

Inventor： See Kei LEE ,  Mitsuo KOIKE ,  Masumi SAITOH

IPC: G01Q70/14 ,  G01Q70/16 ,  G01Q60/58

Abstract: A manufacturing method of a probe according to the present embodiment is used to manufacture a probe for a scanning probe microscope. An insulating film is formed on the surface of a probe provided on a base. Metal ions are implanted into the insulating film. An electric field is applied to the insulating film to concentrate the metal ions in the insulating film at a tip of the probe and form a metallic filament in the insulating film.

公开(公告)号：US20210066316A1

公开(公告)日：2021-03-04

申请号：US16804403

申请日：2020-02-28

Applicant: Kioxia Corporation

Inventor： Kensuke OTA ,  Masumi SAITOH ,  Kiwamu SAKUMA

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11539 ,  H01L27/11529

Abstract: A semiconductor memory device includes a substrate, a plurality of conductive layers, a first semiconductor layer, a memory portion, and a drive circuit which drives the memory cell. The conductive layers are provided in a first region, a second region, and a third region different from the first region and the second region, and a portion positioned in the third region is insulated from a portion positioned in the first region and the second region. The drive circuit is provided in the third region, and includes a second semiconductor layer, and an insulating layer, and one end of the second semiconductor layer is connected to the conductive layers in the second region and the other end of the second semiconductor layer is connected to the substrate.