公开(公告)号：US07286003B2

公开(公告)日：2007-10-23

申请号：US11209351

申请日：2005-08-22

Applicant: Kallol Chatterjee ,  Nitin Agarwal

Inventor： Kallol Chatterjee ,  Nitin Agarwal

IPC: G05F1/10

CPC classification number: G05F3/242 ,  H03K3/356113 ,  H03K17/102

Abstract: An improved on-chip voltage regulator providing improved reliability by eliminating voltage stresses on critical components, comprising, a reference-signal generating block providing a first-order temperature-compensated voltage-reference signal and a first-order temperature-compensated current-reference signal, an operational-amplifier block providing a regulated voltage, connected to the outputs of said reference signal generating block; a standby protection block receiving an external signal for enabling/disabling said reference-signal generating block and said operational-amplifier block, and; a protection voltage block connected to all said blocks; wherein critical elements of said blocks are connected such that voltage difference between any two terminals is always less than the break down voltage of said critical element.

Abstract translation: 一种改进的片上稳压器，通过消除关键部件上的电压应力来提供改进的可靠性，包括：提供一阶温度补偿电压参考信号的参考信号产生模块和一阶温度补偿电流参考信号 提供连接到所述参考信号产生块的输出的调节电压的运算放大器块; 接收外部信号的待机保护块，用于启用/禁用所述参考信号产生块和所述运算放大器块; 连接到所有所述块的保护电压块; 其中所述块的关键元件被连接，使得任何两个端子之间的电压差始终小于所述临界元件的击穿电压。

公开(公告)号：US09444440B2

公开(公告)日：2016-09-13

申请号：US13174574

申请日：2011-06-30

Applicant: Abhishek Jain ,  Kallol Chatterjee ,  Chittoor Parthasarathy ,  Saurabhkumar Singh

Inventor： Abhishek Jain ,  Kallol Chatterjee ,  Chittoor Parthasarathy ,  Saurabhkumar Singh

IPC: H04L7/02 ,  H03K5/1534 ,  H03K19/003

CPC classification number: H03K5/1534 ,  H03K19/00346

Abstract: An embodiment of a detector includes first and second generators. The first generator is operable to receive a transition of a first signal and to generate in response to the transition a first pulse having a length that is approximately equal to a length of a detection window. And the second generator is operable to receive a second signal and to generate a second pulse having a relationship to the first pulse in response to a transition of the second signal occurring approximately during the detection window.

Abstract translation: 检测器的实施例包括第一和第二发生器。 第一发生器可操作以接收第一信号的转换并且响应于转换而产生具有近似等于检测窗口的长度的长度的第一脉冲。 并且第二发生器可操作以响应于在检测窗口期间大致发生的第二信号的转变而接收第二信号并产生与第一脉冲具有关系的第二脉冲。

公开(公告)号：US08552765B2

公开(公告)日：2013-10-08

申请号：US13174078

申请日：2011-06-30

Applicant: Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: G01R29/02

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 我们提出一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US08269545B2

公开(公告)日：2012-09-18

申请号：US13285541

申请日：2011-10-31

Applicant: Nitin Chawla ,  Chittoor Parthasarathy ,  Kallol Chatterjee ,  Promod Kumar

Inventor： Nitin Chawla ,  Chittoor Parthasarathy ,  Kallol Chatterjee ,  Promod Kumar

IPC: H03H11/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

公开(公告)号：US07902885B2

公开(公告)日：2011-03-08

申请号：US12006091

申请日：2007-12-28

Applicant: Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

Inventor： Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

IPC: H03B19/00

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: The disclosure relates a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions.

Abstract translation: 本公开涉及提供改进的转换速率控制的补偿输出缓冲电路和用于最小化缓冲器在过程，电压和温度（PVT）条件下的电流转换速率的变化的方法。 输出缓冲电路包括分闸门补偿驱动器和转换速率控制电路。 因此，可以在PVT条件的宽泛变化范围内以较少的变化来维持期望的转换速率。

公开(公告)号：US07808288B2

公开(公告)日：2010-10-05

申请号：US12006080

申请日：2007-12-28

Applicant: Kallol Chatterjee

Inventor： Kallol Chatterjee

IPC: H03L7/06

CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1293 ,  H03B2200/005 ,  H03L7/087 ,  H03L7/10

Abstract: Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop.

Abstract translation: 用于锁相环（PLL）中的自动粗调的电路和方法包括观察控制电压的变化以禁用精细环路，并且当控制电压偏离指定范围时使能粗环路。 该电路包括微调环路，粗环路和控制电路。 精密回路包括相位频率检测器（PFD），电荷泵，环路滤波器，VCO和分频器。 粗调回路包括频率检测器，向上计数器，向下计数器和LC VCO。 控制电路包括带隙模块，比较器和诸如锁定检测电路的其它电路。 控制电路用于在粗环和微环之间切换。

公开(公告)号：US07598816B2

公开(公告)日：2009-10-06

申请号：US11638306

申请日：2006-12-12

Applicant: Nitin Agarwal ,  Kallol Chatterjee

Inventor： Nitin Agarwal ,  Kallol Chatterjee

IPC: H03L7/08

CPC classification number: H03L7/0891 ,  H03L7/093

Abstract: A phase locked loop (PLL) circuit includes circuitry for preventing an erroneous condition in charge pump operation. The PLL circuit is modified by adding delay elements for connection between the phase frequency detector and the charge pump. A digital logic circuit is also included to provide the clock signals for the loop filter wherein the clock signals have rising edges corresponding to an earlier occurring rising edge of either of the output signals from the phase-frequency detector.

Abstract translation: 锁相环（PLL）电路包括用于防止电荷泵操作中的错误状况的电路。 通过添加用于相位频率检测器和电荷泵之间的连接的延迟元件来修改PLL电路。 还包括数字逻辑电路以提供用于环路滤波器的时钟信号，其中时钟信号具有对应于来自相位 - 频率检测器的任一个输出信号的较早出现的上升沿的上升沿。

公开(公告)号：US20080290915A1

公开(公告)日：2008-11-27

申请号：US12016004

申请日：2008-01-17

Applicant: Kallol Chatterjee ,  Tanmoy Sen

Inventor： Kallol Chatterjee ,  Tanmoy Sen

IPC: H03L7/095

CPC classification number: H03L7/093 ,  H03L7/10

Abstract: A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles.

Abstract translation: 一种用于减少锁相环（PLL）系统的重新锁定时间的系统和方法，该系统包括具有捕获控制电压模块，力控制电压模块，环路滤波器模块和定时器的电路。 捕捉控制电压模块在PLL的锁定时间期间将控制电压（VCO的电压输入）与预定义的电压电平进行比较，并同时存储最接近控制电压的电压电平。 PLL锁定后，存储的电压变得稳定。 在断电被释放后，力控制电压模块会在非常短的时间内强制存储控制电压在环路滤波器上，从而减少PLL的重新锁定时间。 环路滤波器模块稳定控制电压。 然后，定时器在预定义的时钟周期数之后发送超时信号来关闭力控制电压模块。

公开(公告)号：US20080018369A1

公开(公告)日：2008-01-24

申请号：US11649747

申请日：2007-01-03

Applicant: Kallol Chatterjee ,  Nitin Agarwal

Inventor： Kallol Chatterjee ,  Nitin Agarwal

IPC: H03L7/06 ,  H03L7/099

CPC classification number: H03L1/022 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099

Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Abstract translation: 锁相环（PLL）架构提供跨工艺和温度的压控振荡器（VCO）增益补偿。 可以使用模拟器来计算用于处理和温度转角的每个组合的VCO的最大和最小输出频率的控制电压。 然后从这些控制电压中选择控制电压的最大值和最小值。 使用计数器，在PLL输入时钟的一些周期中，VCO的周期数以二进制形式计数，并存储在用于极端控制电压的锁存器中。 它们之间的差异与典型工艺和温度角的相应差异用于修改电荷泵以改变递送到环路滤波器的电流。 电荷泵位决定后，VCO的输入控制电压连接到电荷泵输出，开始PLL的正常工作。

公开(公告)号：US08456195B2

公开(公告)日：2013-06-04

申请号：US13446946

申请日：2012-04-13

Applicant: Kallol Chatterjee ,  Anurag Tiwari

Inventor： Kallol Chatterjee ,  Anurag Tiwari

IPC: H03K9/08

CPC classification number: G01R31/31709

Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract translation: 一种用于测量时钟信号的两个边缘之间的时间间隔的装置，包括边缘发生器，第一多抽头延迟模块，第二多抽头延迟模块和多元件相位检测器。 边缘发生器在第一输出节点处产生第一边缘，并在第二输出节点处产生第二选择边缘。 第一多抽头延迟模块在每个抽头处向第一边缘提供第一增量延迟。 第二多抽头延迟模块在第二选择边缘的每个抽头处提供第二增量延迟。 多元件相位检测器的每个元件具有第一和第二输入端子。 第一输入端耦合到第一多抽头延迟模块的选定抽头，第二输入端耦合到第二多抽头延迟模块的对应抽头。 多元件相位检测器的输出端提供时间间隔的值。