公开(公告)号：US20120218002A1

公开(公告)日：2012-08-30

申请号：US13446946

申请日：2012-04-13

Applicant: Kallol Chatterjee ,  Anurag Tiwari

Inventor： Kallol Chatterjee ,  Anurag Tiwari

IPC: G01R29/02

CPC classification number: G01R31/31709

Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract translation: 一种用于测量时钟信号的两个边缘之间的时间间隔的装置，包括边缘发生器，第一多抽头延迟模块，第二多抽头延迟模块和多元件相位检测器。 边缘发生器在第一输出节点处产生第一边缘，并在第二输出节点处产生第二选择边缘。 第一多抽头延迟模块在每个抽头处向第一边缘提供第一增量延迟。 第二多抽头延迟模块在第二选择边缘的每个抽头处提供第二增量延迟。 多元件相位检测器的每个元件具有第一和第二输入端子。 第一输入端耦合到第一多抽头延迟模块的选定抽头，第二输入端耦合到第二多抽头延迟模块的对应抽头。 多元件相位检测器的输出端提供时间间隔的值。

公开(公告)号：US20110001458A1

公开(公告)日：2011-01-06

申请号：US12698328

申请日：2010-02-02

Applicant: Nitin Bansal ,  Kallol Chatterjee

Inventor： Nitin Bansal ,  Kallol Chatterjee

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: Described herein are principles for designing and operating a voltage regulator that will function stably and accurately without an external capacitance for all or a wide range of load circuits and characteristics of load circuits. In accordance with some of these principles, a voltage regulator is disclosed having multiple feedback loops, each responding to transients with different speeds, that operate in parallel to adjust an output current of the regulator in response to variations in the output current/voltage due to, for example, variations in a supply voltage and/or variations in a load current. In this way, a voltage regulator can respond quickly to variations in the output current/voltage and can avoid entering an unstable state.

Abstract translation: 这里描述的是用于设计和操作电压调节器的原理，其将稳定且准确地运行，而无需外部电容用于所有或宽范围的负载电路和负载电路的特性。 根据这些原理中的一些，公开了一种电压调节器，其具有多个反馈回路，每个响应于不同速度的瞬变，其并联操作以响应于由于输出电流/电压的变化而调节调节器的输出电流 ，例如，电源电压的变化和/或负载电流的变化。 以这种方式，电压调节器可以快速响应输出电流/电压的变化，并且可以避免进入不稳定状态。

公开(公告)号：US07663415B2

公开(公告)日：2010-02-16

申请号：US11649747

申请日：2007-01-03

Applicant: Kallol Chatterjee ,  Nitin Agarwal

Inventor： Kallol Chatterjee ,  Nitin Agarwal

IPC: H03L7/06

CPC classification number: H03L1/022 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099

Abstract: A phase locked loop (PLL) architecture provides voltage controlled oscillator (VCO) gain compensation across process and temperature. A simulator may be used to calculate the control voltages for the maximum and minimum output frequency of the VCO for each combination of the process and temperature corners. The maximum and minimum values of control voltage are then selected from these control voltages. Using a counter, the number of cycles of VCO in some cycles of the PLL input clock are counted in binary form and stored in latches for the extreme control voltages. The difference between them and the corresponding difference for typical process and temperature corner is used to modify the charge pump to change the current delivered to the loop filter. After the charge pump bits have been decided, the input control voltage of the VCO connects to the charge pump output to start the normal operation of the PLL.

Abstract translation: 锁相环（PLL）架构提供跨工艺和温度的压控振荡器（VCO）增益补偿。 可以使用模拟器来计算用于处理和温度转角的每个组合的VCO的最大和最小输出频率的控制电压。 然后从这些控制电压中选择控制电压的最大值和最小值。 使用计数器，在PLL输入时钟的一些周期中，VCO的周期数以二进制形式计数，并存储在用于极端控制电压的锁存器中。 它们之间的差异与典型工艺和温度角的相应差异用于修改电荷泵以改变递送到环路滤波器的电流。 电荷泵位决定后，VCO的输入控制电压连接到电荷泵输出，开始PLL的正常工作。

公开(公告)号：US20090091358A1

公开(公告)日：2009-04-09

申请号：US12006091

申请日：2007-12-28

Applicant: Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

Inventor： Vijender Singh Chauhan ,  Kallol Chatterjee ,  Paras Garg

IPC: H03B1/00

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: The present invention provides a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit includes a split-gate compensated driver and a slew rate control circuit. Accordingly, a desired slew rate can be maintained with fewer variations over wide range of variations in PVT conditions. The slew rate control circuit consists of two separate slew rate control circuits called a pull-up PMOS driver and a pull-down NMOS driver. To minimize the variations in the slew rate, the rising and falling time of the pre-driver nodes are controlled by means of two current control networks, which are compensated against PVT variations by using separate NMOS and PMOS digital compensation codes. The compensation codes are provided by a compensation circuit, which sense the variation in PVT conditions and reflect these variations in the compensation codes.

Abstract translation: 本发明提供一种补偿输出缓冲电路，其提供改进的转换速率控制和用于最小化缓冲器在过程，电压和温度（PVT）条件下的电流转换速率的变化的方法。 输出缓冲电路包括分闸门补偿驱动器和转换速率控制电路。 因此，可以在PVT条件的宽泛变化范围内以较少的变化来维持期望的转换速率。 转换速率控制电路由两个单独的转换速率控制电路组成，称为上拉PMOS驱动器和下拉式NMOS驱动器。 为了最小化转换速率的变化，预驱动器节点的上升和下降时间通过两个电流控制网络来控制，这两个电流控制网络通过使用单独的NMOS和PMOS数字补偿代码来补偿PVT变化。 补偿代码由补偿电路提供，该补偿电路检测PVT条件的变化并反映补偿代码中的这些变化。

公开(公告)号：US20120158339A1

公开(公告)日：2012-06-21

申请号：US12974409

申请日：2010-12-21

Applicant: Nitin Chawla ,  Kallol Chatterjee ,  Chittoor Parthasarathy

Inventor： Nitin Chawla ,  Kallol Chatterjee ,  Chittoor Parthasarathy

IPC: G06F19/00

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3024 ,  G06F11/3058 ,  G11C29/023 ,  Y02D10/126 ,  Y02D10/172

Abstract: An arrangement including at least one path, at least one replica path, the at least one replica path corresponding to a respective path, a controller configured to use control information derived from the at least one replica path, at least one of the paths comprising a monitoring unit configured to provide monitor information to the controller, the controller being configured to modify the control information in dependence on the monitor information.

Abstract translation: 包括至少一个路径，至少一个复制路径，对应于相应路径的所述至少一个复制路径的布置，被配置为使用从所述至少一个复制路径导出的控制信息的控制器，所述至少一个路径包括 监视单元，被配置为向所述控制器提供监视器信息，所述控制器被配置为根据所述监视器信息修改所述控制信息。

公开(公告)号：US20110068858A1

公开(公告)日：2011-03-24

申请号：US12563058

申请日：2009-09-18

Applicant: Nitin Chawla ,  Chittoor Parthasarathy ,  Kallol Chatterjee ,  Promod Kumar

Inventor： Nitin Chawla ,  Chittoor Parthasarathy ,  Kallol Chatterjee ,  Promod Kumar

IPC: G05F1/10

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract translation: 片上系统（SoC）具有数字域。 自适应电压/频率缩放电路包括关于该数字域的关键路径复制电路。 关键路径复制电路产生余量信号，并且自适应电压调节电路通过减少施加到片上系统的数字域的偏置电压（和/或增加时钟频率）来响应余量信号，以便恢复可用余量。 故障安全定时传感器包括在片上系统的数字域中。 当数字域内的定时标准被违反时，定时传感器产生一个标志信号。 自适应电压缩放电路通过增加施加到片上系统的数字域的偏置电压（和/或降低时钟频率）来响应标志信号，以便实现恢复操作。

公开(公告)号：US20100019757A1

公开(公告)日：2010-01-28

申请号：US12507686

申请日：2009-07-22

Applicant: Anurag Ramesh Tiwari ,  Kallol Chatterjee

Inventor： Anurag Ramesh Tiwari ,  Kallol Chatterjee

IPC: G01R23/16

CPC classification number: G01R31/31727

Abstract: An apparatus and method for measuring the duty cycle of a clock signal, the apparatus having a first multi-tap delay module, a second multi-tap delay module, and a multi-element detecting module, the input terminal of the first multi-tap delay module and the input terminal of the second multi-tap delay module coupled to an input node IN, the first multi-tap delay module receiving the clock signal and then providing it a first constant incremental delay at each tap, the second multi-tap delay module receiving the same clock signal CLK and then providing it a second constant incremental delay at each tap, and the multi-element detecting module determining the ratio of the number of outputs of the multi-element detecting module in which the sampled clock level is high with respect to the total number of steps covering one complete clock cycle.

Abstract translation: 一种用于测量时钟信号的占空比的装置和方法，该装置具有第一多抽头延迟模块，第二多抽头延迟模块和多元件检测模块，第一多抽头的输入端 延迟模块和耦合到输入节点IN的第二多抽头延迟模块的输入端，第一多抽头延迟模块接收时钟信号，然后在每个抽头提供第一恒定的增量延迟，第二多抽头 延迟模块接收相同的时钟信号CLK，然后在每个抽头提供第二恒定的增量延迟，并且多元素检测模块确定多元素检测模块的输出数量，其中采样时钟电平为 相对于涵盖一个完整时钟周期的总步数来说是高的。

公开(公告)号：US07489205B2

公开(公告)日：2009-02-10

申请号：US11146930

申请日：2005-06-06

Applicant: Kallol Chatterjee ,  Samala Sreekiran

Inventor： Kallol Chatterjee ,  Samala Sreekiran

IPC: H03L7/00

CPC classification number: H03L7/0995 ,  H03L7/18

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.

Abstract translation: 一种VCO缓冲电路，包括第一加载装置，其接收用于在第一输入节点加载VCO的第一信号; 第二加载装置，在第二输入节点处接收用于加载所述VCO的第二信号; 耦合到所述第一加载装置的第三加载装置，用于在第三输入节点处加载VCO，从而平衡VCO的三个节点上的负载分布。 至少三个电流控制装置彼此耦合以形成对称配置，并且从所述第一和第二负载装置接收输入信号，以最小化VCO振荡频率的变化。 缓冲装置连接到控制装置的输出端，用于缓冲电流控制装置的输出。

公开(公告)号：US20080238505A1

公开(公告)日：2008-10-02

申请号：US12006080

申请日：2007-12-28

Applicant: Kallol Chatterjee

Inventor： Kallol Chatterjee

IPC: H03L7/06 ,  H03B5/18 ,  H04B1/40

CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1293 ,  H03B2200/005 ,  H03L7/087 ,  H03L7/10

Abstract: Circuits and methods for an automatic coarse tuning in a phase locked loop (PLL) include observing a variation in a control voltage to disable a fine loop and to enable a coarse loop as the control voltage departs from a specified range. The circuit includes the fine loop, the coarse loop, and a control circuit. The fine loop includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO and a divider. The coarse loop includes a frequency detector, an up counter, a down counter, and an LC VCO. The control circuit includes a bandgap module, a comparator and other circuits such as a lock detect circuit. The control circuit is used to switch between the coarse loop and the fine loop.

Abstract translation: 用于锁相环（PLL）中的自动粗调的电路和方法包括观察控制电压的变化以禁用精细环路，并且当控制电压偏离指定范围时使能粗环路。 该电路包括微调环路，粗环路和控制电路。 精密回路包括相位频率检测器（PFD），电荷泵，环路滤波器，VCO和分频器。 粗调回路包括频率检测器，向上计数器，向下计数器和LC VCO。 控制电路包括带隙模块，比较器和诸如锁定检测电路的其它电路。 控制电路用于在粗环和微环之间切换。

公开(公告)号：US07372316B2

公开(公告)日：2008-05-13

申请号：US11286276

申请日：2005-11-22

Applicant: Kallol Chatterjee ,  Samala Sreekiran

Inventor： Kallol Chatterjee ,  Samala Sreekiran

IPC: H03K3/42

CPC classification number: G05F3/242

Abstract: A first order temperature compensated reference current generator includes a current device providing a controlled current, a startup circuit connected to the current device for initiating operation of the current device, and a current definition mechanism driven by the current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

Abstract translation: 第一阶温度补偿参考电流发生器包括提供受控电流的电流装置，连接到当前装置的启动电路，用于启动当前装置的操作，以及由当前装置驱动的用于提供独立电流的电流的电流定义机构 的温度，工艺和各个温度系数电路元件。 目前的定义机构包含由预定电压驱动并具有预定温度系数的压控电阻。