-
公开(公告)号：US20120025282A1
公开(公告)日：2012-02-02
申请号：US12848494
申请日：2010-08-02
IPC分类号： H01L29/94 , H01L27/088 , H01L21/336 , H01L27/105
CPC分类号： H01L27/1203 , H01L21/823418 , H01L21/823425 , H01L21/84 , H01L29/66628
摘要： In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.
-
12.发明申请STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权具有单个间距的垂直源/源压应力的应变薄体CMOS器件公开(公告)号：US20110309446A1
公开(公告)日：2011-12-22
申请号：US12816399
申请日：2010-06-16
IPC分类号： H01L27/12 , H01L21/8238 , H01L29/786 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。
-
公开(公告)号：US09054211B2
公开(公告)日：2015-06-09
申请号：US13540801
申请日：2012-07-03
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。
-
公开(公告)号：US08994085B2
公开(公告)日：2015-03-31
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
摘要翻译： 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。
-
公开(公告)号：US08653596B2
公开(公告)日：2014-02-18
申请号：US13344885
申请日：2012-01-06
IPC分类号： H01L21/70 , H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1052 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/1116 , H01L27/1203 , H01L27/1207
摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
摘要翻译： 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。
-
公开(公告)号：US20130344677A1
公开(公告)日：2013-12-26
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
-
公开(公告)号：US20130341754A1
公开(公告)日：2013-12-26
申请号：US13531654
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.
-
公开(公告)号：US20130270627A1
公开(公告)日：2013-10-17
申请号：US13444219
申请日：2012-04-11
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/28273 , H01L21/28282 , H01L21/845 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1157 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.
摘要翻译： 一种制造FinFET非易失性存储器件和FinFET非易失性存储器件结构的方法。 提供衬底并且在衬底上沉积半导体材料层。 在半导体材料上沉积硬掩模，并且将该结构图案化以形成翅片。 电荷存储层沉积在结构上，包括鳍片，并且其部分使用成角度的离子注入工艺被损坏。 损坏的部分被去除并且栅极结构形成在翅片的任一侧，只有一侧具有电荷存储层。
-
19.发明授权Strained thin body CMOS device having vertically raised source/drain stressors with single spacer 有权应变的薄体CMOS器件具有单个间隔物的垂直升高的源/漏应力源公开(公告)号：US08546228B2
公开(公告)日：2013-10-01
申请号：US12816399
申请日：2010-06-16
IPC分类号： H01L21/336
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。
-
公开(公告)号：US20130175595A1
公开(公告)日：2013-07-11
申请号：US13344885
申请日：2012-01-06
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1052 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/1116 , H01L27/1203 , H01L27/1207
摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
摘要翻译： 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。
-
-
-
-
-
-
-
-
-
搜索结果
506 条记录 (耗时 0.027 秒)
