公开(公告)号：US20080213993A1

公开(公告)日：2008-09-04

申请号：US12098976

申请日：2008-04-07

申请人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

发明人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

公开(公告)号：US07060619B2

公开(公告)日：2006-06-13

申请号：US10379346

申请日：2003-03-04

申请人： Andy Cowley ,  Erdem Kaltalioglu ,  Mark Hoinkis ,  Michael Stetter

发明人： Andy Cowley ,  Erdem Kaltalioglu ,  Mark Hoinkis ,  Michael Stetter

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76877

摘要： Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

摘要翻译： 形成包含逻辑电路（微处理器，Asics或其他）或随机存取存储器单元（DRAMS）的半导体主体上的互连层以显着减少相邻导体/通孔之间的短路数量的方式形成， 0.18微米或更小。 这是通过蚀刻完成的，以在化学机械抛光工艺完成后在每一层上形成凹陷的铜顶表面。 在凹陷的铜表面上施加的阻挡层的厚度被控制成与周围的绝缘体表面基本上共面。 较厚的阻挡层消除了对覆盖层的需要。 消除覆盖层导致整体电容耦合，应力和成本的降低。

公开(公告)号：US07368804B2

公开(公告)日：2008-05-06

申请号：US10439874

申请日：2003-05-16

申请人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

发明人： Mark Hoinkis ,  Matthias Hierlemann ,  Gerald Friese ,  Andy Cowley ,  Dennis J. Warner ,  Erdem Kaltalioglu

IPC分类号： H01L23/58 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

摘要翻译： 提供了一种方法，装置和系统，用于在通孔下方的线宽大于基准规则时，减少半导体结构的通孔结构中的应力，包括提供至少与基底层一样大的通孔， 通孔，提供通孔条来代替通孔，将通孔下方的金属线宽开槽，或者提供具有侧壁间隔物的超尺寸通孔。

公开(公告)号：US06638851B2

公开(公告)日：2003-10-28

申请号：US09845305

申请日：2001-05-01

申请人： Andy Cowley ,  Erdem Kaltalioglu ,  Michael Stetter

发明人： Andy Cowley ,  Erdem Kaltalioglu ,  Michael Stetter

IPC分类号： H01L214763

CPC分类号： H01L21/76802

摘要： Process of making a semiconductor using dual inorganic hardmask in single damascene process integration scheme in an organic low k interlayer dielectric (ILD) by: providing semiconductor substrate; depositing organic low k ILD layer on substrate; forming hardmask 1 on organic low k ILD layer and forming sacrificial hardmask 2 on hardmask 1; forming a patterned photoresist layer on sacrificial hardmask 2; etching selective to sacrificial hardmask 2 and stripping photoresist; etching of hardmask 1 in which the etch is selective to the organic low k ILD layer; depositing a liner or conformal barrier layer over the substrate, organic low k ILD layer, hardmask 1 and hardmask 2; forming a plated metal layer over the liner or conformal barrier layer; and removing metal layer and removing liner with simultaneous removal of sacrificial hardmask 2 so that facets in sacrificial hardmask 2 are removed during liner/sacrificial hardmask 2 removal.

摘要翻译： 在有机低k层间电介质（ILD）中的单镶嵌工艺集成方案中使用双重无机硬掩模制造半导体的工艺：提供半导体衬底;在衬底上沉积有机低k ILD层;在有机低k ILD层上形成硬掩模1; 在硬掩模1上形成牺牲硬掩模2;在牺牲硬掩模2上形成图案化的光刻胶层;对牺牲硬掩模2进行选择性蚀刻和剥离光刻胶;蚀刻硬掩模1，其中蚀刻对有机低k ILD层是选择性的;沉积衬垫或 在衬底上的共形阻挡层，有机低k ILD层，硬掩模1和硬掩模2;在衬里或保形阻挡层上形成电镀金属层; 并移除金属层，同时去除牺牲性硬掩模2，从而在衬垫/牺牲硬掩模2移除期间去除牺牲硬掩模2中的刻面。

公开(公告)号：US06806579B2

公开(公告)日：2004-10-19

申请号：US10364190

申请日：2003-02-11

申请人： Andy Cowley ,  Michael Stetter ,  Erdem Kaltalioglu

发明人： Andy Cowley ,  Michael Stetter ,  Erdem Kaltalioglu

IPC分类号： H01L2144

CPC分类号： H01L21/76802 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

摘要翻译： 在第一绝缘层中形成导线。 在导电线和第一绝缘层上形成第二绝缘层。 通孔延伸穿过第二绝缘层以至少接触导电线的顶表面。 通孔还延伸穿过第一绝缘层以接触导电线的至少一个侧壁的至少顶部。 导电线侧壁可以包括向外延伸的钩区域，使得通孔的一部分设置在导线钩区域下方，在接近导线钩区域的通孔内形成锁定区域。

公开(公告)号：US06784105B1

公开(公告)日：2004-08-31

申请号：US10410496

申请日：2003-04-09

申请人： Chih-Chao Yang ,  Yun Wang ,  Larry Clevenger ,  Andrew Simon ,  Stephen Greco ,  Kaushik Chanda ,  Terry Spooner ,  Andy Cowley ,  Sunfei Fang

发明人： Chih-Chao Yang ,  Yun Wang ,  Larry Clevenger ,  Andrew Simon ,  Stephen Greco ,  Kaushik Chanda ,  Terry Spooner ,  Andy Cowley ,  Sunfei Fang

IPC分类号： H01L2144

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76838 ,  H01L21/76862 ,  H01L21/76865

摘要： A method of fabricating a semiconductor device having a dielectric structure on which an interconnect structure is optionally patterned using lithographic and etching techniques, within a single deposition chamber, is provided. The dielectric structure may optionally be covered by diffusion barrier materials prior to a sputter etching process. This sputter etching process is used to remove the native oxide on an underneath metal conductor surface and includes a directional gaseous bombardment with simultaneous deposition of metal neutral. Diffusion barrier materials may also be deposited into the pattern.

摘要翻译： 提供一种制造具有电介质结构的半导体器件的方法，其中使用光刻和蚀刻技术在单个淀积室内使互连结构任意地图案化。 在溅射蚀刻工艺之前，电介质结构可任选地被扩散阻挡材料覆盖。 该溅射蚀刻工艺用于去除下面的金属导体表面上的自然氧化物，并且包括具有同时沉积金属中性的定向气体轰击。 扩散阻挡材料也可以沉积到图案中。

公开(公告)号：US06758223B1

公开(公告)日：2004-07-06

申请号：US09603254

申请日：2000-06-23

申请人： Andy Cowley ,  Peter Emmi ,  Timothy Dalton ,  Christopher Jahnes

发明人： Andy Cowley ,  Peter Emmi ,  Timothy Dalton ,  Christopher Jahnes

IPC分类号： B08B600

CPC分类号： H01L21/02063 ,  H01L21/31138 ,  H01L21/76804 ,  H01L21/76807 ,  Y10S134/902 ,  Y10S438/906

摘要： A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising: supplying a reducing gas plasma incorporating a forming gas mixture selected from the group consisting of a mixture of N2/H2 or a mixture of NH3/H2 into a vacuum chamber in which a semiconductor wafer surface or a microelectronic composite structure is supported to form a post-RIE polymer material by-product on the composite structure without significant removal of an organic, low K material which has also been exposed to the reducing gas plasma; and removing the post-RIE polymer material by-product with a wet clean.

摘要翻译： 一种用于从半导体晶片表面或微电子复合结构去除后反应离子蚀刻副产物的方法，包括：提供还原气体等离子体，该还原气体等离子体包含选自N2 / H2或NH3混合物的成形气体混合物 / H2进入真空室，其中半导体晶片表面或微电子复合结构被支撑以在复合结构上形成后RIE聚合物材料副产物，而不显着除去已经暴露于 还原气体等离子体; 并用湿式清洁剂除去后RIE聚合物材料副产物。

公开(公告)号：US07041574B2

公开(公告)日：2006-05-09

申请号：US10894259

申请日：2004-07-19

申请人： Sun-Oo Kim ,  Markus Naujok ,  Andy Cowley

发明人： Sun-Oo Kim ,  Markus Naujok ,  Andy Cowley

IPC分类号： H01L21/76

CPC分类号： H01L21/76829 ,  H01L21/76835 ,  H01L21/76885 ,  Y10S438/958

摘要： A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.

摘要翻译： 提供了形成复合金属间电介质结构的方法。 提供初始的金属间电介质结构，其包括第一介电层和两条导线。 两条导线位于第一介质层中。 第一介电层的一部分在导线之间被去除以形成沟槽。 沟槽填充有第二电介质材料。 第二电介质材料是具有小于第一介电层的介电常数的介电常数的低k电介质。

公开(公告)号：US06864171B1

公开(公告)日：2005-03-08

申请号：US10682462

申请日：2003-10-09

申请人： Mark D. Hoinkis ,  Matthias P. Hierlemann ,  Mohammed Fazil Fayaz ,  Andy Cowley ,  Erdum Kaltalioglu

发明人： Mark D. Hoinkis ,  Matthias P. Hierlemann ,  Mohammed Fazil Fayaz ,  Andy Cowley ,  Erdum Kaltalioglu

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.

摘要翻译： 通孔上的热机械应力降低，从而减少相关故障。 这可以通过保持通孔至金属面积比至少等于预定值以下，通孔上的附加应力不会显着增加的程度来实现。

公开(公告)号：US06872648B2

公开(公告)日：2005-03-29

申请号：US10246999

申请日：2002-09-19

申请人： Gerald R. Friese ,  Andy Cowley ,  Mohammed Fazil Fayaz ,  William T. Motsiff

发明人： Gerald R. Friese ,  Andy Cowley ,  Mohammed Fazil Fayaz ,  William T. Motsiff

IPC分类号： H01L23/525 ,  H01L21/71

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The act of blowing an unpassivated electrical fuse (for example, fuse 405) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier 406) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.

摘要翻译： 使用激光器吹动未激活的电熔丝（例如，熔丝405）的行为可能导致熔丝材料的飞溅并导致电气短路。 形成在由激光器熔断的熔丝区域周围形成的防爆屏障（例如鼓风屏障406）有助于容纳熔丝材料的飞溅。 防爆屏障可以由与熔丝本身相同的材料形成，因此可以在相同的制造步骤中形成。