公开(公告)号：US07824976B2

公开(公告)日：2010-11-02

申请号：US12654559

申请日：2009-12-23

申请人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

发明人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

IPC分类号： H01L21/8249

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/78

摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

摘要翻译： 一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极 高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种，以SiO 2为主要成分的膜和N，以SiO 2为主要成分的膜，Hf和N，含有SiO 2作为 主成分Zr和N，或以SiO2为主要成分的膜，Hf，Zr和N.

公开(公告)号：US07501335B2

公开(公告)日：2009-03-10

申请号：US10999937

申请日：2004-12-01

申请人： Katsuyuki Sekine ,  Yoshitaka Tsunashima ,  Seiji Inumiya ,  Akio Kaneko ,  Motoyuki Sato ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Yoshitaka Tsunashima ,  Seiji Inumiya ,  Akio Kaneko ,  Motoyuki Sato ,  Kazuhiro Eguchi

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/469

CPC分类号： H01L21/02321 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/022 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3143 ,  H01L21/31645 ,  H01L29/518

摘要： A manufacturing method of a semiconductor device disclosed herein, comprises: forming a silicate film containing metal on a substrate; and introducing nitrogen and deuterium into the silicate film by using ND3 gas.

摘要翻译： 本文公开的半导体器件的制造方法包括：在基板上形成含有金属的硅酸盐膜; 并通过使用ND3气体将氮和氘引入硅酸盐膜。

公开(公告)号：US20090000547A1

公开(公告)日：2009-01-01

申请号：US12222679

申请日：2008-08-14

申请人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

IPC分类号： B05C11/00 ,  C23C16/00

CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67069 ,  H01L22/14

摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising:measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma;calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; andexposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.

摘要翻译： 根据本发明，提供了一种半导体器件的制造方法，其特征在于，当对等离子体发射的光中包含的至少一种类型的波长的发光强度进行测量时，当氮化，氧化和杂质掺杂之一将对 通过使用等离子体在处理容器中的半导体衬底的表面; 基于所测量的发光强度，针对每个半导体衬底计算半导体衬底暴露于等离子体的曝光时间; 并根据计算出的曝光时间将各半导体衬底暴露于等离子体，从而进行氮化，氧化和杂质掺杂之一。

公开(公告)号：US20080265324A1

公开(公告)日：2008-10-30

申请号：US12081824

申请日：2008-04-22

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L29/786

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

公开(公告)号：US07427518B2

公开(公告)日：2008-09-23

申请号：US11260253

申请日：2005-10-28

申请人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Seiji Inumiya ,  Motoyuki Sato ,  Akio Kaneko ,  Kazuhiro Eguchi

IPC分类号： H01L21/00

CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67069 ,  H01L22/14

摘要： According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.

摘要翻译： 根据本发明，提供了一种半导体器件的制造方法，其特征在于，当对等离子体发射的光中包含的至少一种类型的波长的发光强度进行测量时，当氮化，氧化和杂质掺杂之一将对 通过使用等离子体在处理容器中的半导体衬底的表面; 基于所测量的发光强度，针对每个半导体衬底计算半导体衬底暴露于等离子体的曝光时间; 并根据计算出的曝光时间将各半导体衬底暴露于等离子体，从而进行氮化，氧化和杂质掺杂之一。

公开(公告)号：US20070197048A1

公开(公告)日：2007-08-23

申请号：US11785606

申请日：2007-04-19

申请人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

IPC分类号： H01L21/31

CPC分类号： C23C16/401 ,  C23C16/56 ,  H01L21/02329 ,  H01L21/3145

摘要： According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：选择性地形成在半导体衬底的预定区域上的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及在所述半导体衬底的表面部分中形成在位于所述栅极电极下方的沟道区域的两侧上的源极区和漏极区，其中所述栅极绝缘膜与所述栅电极接触的界面中的碳浓度 不大于5×10 22个原子/ cm 3。

公开(公告)号：US07242363B2

公开(公告)日：2007-07-10

申请号：US10819259

申请日：2004-04-07

申请人： Munenori Fujimura ,  Shuichiro Yamaguchi ,  Hiromi Tokunaga ,  Kazuhiro Eguchi

发明人： Munenori Fujimura ,  Shuichiro Yamaguchi ,  Hiromi Tokunaga ,  Kazuhiro Eguchi

IPC分类号： H01Q1/36 ,  H01Q21/00

CPC分类号： G06F1/1698 ,  G06F1/1616 ,  G06F1/1626 ,  H01Q1/2258 ,  H01Q1/2266 ,  H01Q1/243 ,  H01Q1/362 ,  H01Q1/40 ,  H01Q3/06 ,  H01Q3/2623 ,  H01Q9/16 ,  H01Q9/28 ,  H01Q9/46 ,  H01Q11/08 ,  H01Q13/10 ,  H01Q21/29

摘要： An antenna element, an antenna module, and an electronic equipment using these, are small-sized, high in transmitting and receiving performance, and capable of transmitting and receiving electric waves at a plurality of frequencies. The antenna element includes two antennas having at least a feeder portion and an open portion, and current is fed to each feeder portion. The antenna module includes at least an antenna and a mounting body in which the antenna is mounted, and current is fed to each feeder portion. The electronic equipment includes at least the antenna element or antenna module, a signal modulator, a signal demodulator, a controller, a man-machine interface, and a casing.

摘要翻译： 使用这些的天线元件，天线模块和电子设备是小型的，高的发送和接收性能，并且能够以多个频率发送和接收电波。 天线元件包括至少具有馈电部分和开放部分的两个天线，并且电流馈送到每个馈送部分。 天线模块至少包括天线和天线安装在其中的安装体，并且电流被馈送到每个馈送部分。 电子设备至少包括天线元件或天线模块，信号调制器，信号解调器，控制器，人机界面和外壳。

公开(公告)号：US07101775B2

公开(公告)日：2006-09-05

申请号：US10911516

申请日：2004-08-05

申请人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

发明人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

IPC分类号： H01L21/3205

CPC分类号： H01L29/511 ,  C23C16/30 ,  C23C16/45523 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28229 ,  H01L21/31604 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.

公开(公告)号：US20050158932A1

公开(公告)日：2005-07-21

申请号：US10995296

申请日：2004-11-24

申请人： Seiji Inumiya ,  Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Yoshitaka Tsunashima

发明人： Seiji Inumiya ,  Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Yoshitaka Tsunashima

IPC分类号： H01L29/423 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/31 ,  H01L21/8234

CPC分类号： H01L29/6656 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： A method of manufacturing a semiconductor device, comprises: providing a gate insulation layer of a high dielectric constant containing a metal element on a surface of a semiconductor substrate, part of which becoming a channel; providing a first conductive layer containing a silicon element on the surface of said gate insulation layer, said first conductive layer being a gate electrode; and introducing nitrogen or oxygen onto an interface between said gate insulation layer and said first conductive layer by executing a thermal treatment upon said semiconductor substrate in a atmosphere containing a nitriding agent or an oxidizing agent.

摘要翻译： 一种制造半导体器件的方法，包括：在半导体衬底的表面上提供包含金属元素的高介电常数的栅极绝缘层，其中一部分变成沟道; 在所述栅极绝缘层的表面上提供含有硅元素的第一导电层，所述第一导电层是栅电极; 以及通过在包含氮化剂或氧化剂的气氛中对所述半导体衬底进行热处理，将氮或氧引入到所述栅极绝缘层和所述第一导电层之间的界面上。

公开(公告)号：US06844234B2

公开(公告)日：2005-01-18

申请号：US10101913

申请日：2002-03-21

申请人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

发明人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

IPC分类号： H01L21/31 ,  C23C16/30 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/511 ,  C23C16/30 ,  C23C16/45523 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28229 ,  H01L21/31604 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.

摘要翻译： 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上并包括含有金属元素的氧化硅膜的栅极电介质，所述氧化硅膜含有所述金属元素，所述金属元素包括在其下表面附近的第一区域， 上表面和第一和第二区域之间的第三区域，包含在氧化硅膜中的金属元素在氧化硅膜的厚度方向上具有密度分布，存在于第三区域中的密度分布的峰值， 以及形成在栅极电介质上的电极。