公开(公告)号：US06243032B1

公开(公告)日：2001-06-05

申请号：US09399368

申请日：1999-09-20

申请人： Shinichi Uramoto ,  Tetsuya Hara

发明人： Shinichi Uramoto ,  Tetsuya Hara

IPC分类号： H03M100

CPC分类号： G11B20/00007 ,  G11B20/00086 ,  G11B20/10527

摘要： An A/V signal pickup unit receives an audio digital data stream. A CPU carries out a decode process, and adds tag data indicating the attribute of audio sample data to provide the same to an audio signal converter unit. The audio signal converter unit controls the timing of the output operation of sample data according to the tag data.

摘要翻译： A / V信号拾取单元接收音频数字数据流。 CPU执行解码处理，并且添加指示音频采样数据的属性的标签数据以将其提供给音频信号转换器单元。 音频信号转换器单元根据标签数据控制采样数据的输出操作的定时。

公开(公告)号：US5699117A

公开(公告)日：1997-12-16

申请号：US601273

申请日：1996-02-14

申请人： Shinichi Uramoto ,  Akihiko Takabatake

发明人： Shinichi Uramoto ,  Akihiko Takabatake

IPC分类号： H04N19/50 ,  G06T9/00 ,  H03M7/00 ,  H03M7/36 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/503 ,  H04N19/577 ,  H04N19/587 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/65 ,  H04N19/70 ,  H04N19/80 ,  H04N19/89 ,  H04N19/895 ,  H04N19/91 ,  H04N19/93 ,  H04N7/26

CPC分类号： H04N19/895 ,  H04N19/174 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N19/70 ,  H04N19/13 ,  H04N19/91

摘要： When a macro block synchronizing signal indicating starting of processing is asserted in processing of one processing section which is formed by a macro block header and a macro block, block data of the macro block are decoded in synchronization with the assertion of MBSYNC, and next macro block header information is analyzed in continuation in the processing section. The assertion of the next MB synchronizing signal is stopped until prescribed conditions are established. Processing of the block data of the macro blocks is regularly executed from starting of one processing section, whereby utilization efficiency of operational processors is improved.

摘要翻译： 当在由宏块头部和宏块形成的一个处理部分的处理中确定指示开始处理的宏块同步信号时，宏块的块数据与MBSYNC的断言同步地被解码，下一个宏 在处理部分中继续分析块头信息。 停止下一个MB同步信号的断言，直到建立规定的条件。 从一个处理部分的开始定期执行宏块的块数据的处理，从而提高了操作处理器的利用效率。

公开(公告)号：US5497340A

公开(公告)日：1996-03-05

申请号：US75911

申请日：1993-06-14

申请人： Shinichi Uramoto ,  Hideyuki Terane

发明人： Shinichi Uramoto ,  Hideyuki Terane

IPC分类号： G06F7/38 ,  G06F5/01

CPC分类号： G06F5/01

摘要： A data comparator detects the coincidence or non-coincidence of the logical states between two adjacent bits of the plural bit input data and applies the comparison result signal to a non-coincident bit detection circuit. A mask generator decodes a shift select signal indicating the amount of shift to produce mask data and applies the produced mask data to a non-coincident bit detection circuit. The non-coincident bit detection circuit masks the output of the data comparator on the basis of the mask data and decides whether or not an overflow is produced from the masked output of the data comparator to output the result of decision.

摘要翻译： 数据比较器检测多位输入数据的两个相邻位之间的逻辑状态的一致或非重合，并将比较结果信号施加到非重合位检测电路。 掩模发生器解码表示移位量的移位选择信号以产生掩模数据，并将所产生的掩模数据施加到非重合位检测电路。 非重合位检测电路根据掩模数据对数据比较器的输出进行掩蔽，并判定是否从数据比较器的被屏蔽输出产生溢出，以输出判定结果。

公开(公告)号：US5249146A

公开(公告)日：1993-09-28

申请号：US854922

申请日：1992-03-20

申请人： Shinichi Uramoto ,  Yoshitsugu Inoue

发明人： Shinichi Uramoto ,  Yoshitsugu Inoue

IPC分类号： G06F7/548 ,  G06F1/035 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20 ,  G06T9/00

CPC分类号： G06F17/147 ,  G06F1/0356 ,  G06T9/007 ,  G06F2101/02

摘要： A one-dimensional discrete cosine transform processor of N (N: positive integer)-term input data X includes a preprocessing section for carrying out addition and subtraction of (i)th-term data x (i) and (N-i)th-term data x (N-1) of input data X, and a unit for performing a product sum operation for sets of intermediate data subjected to preprocessing by addition and sets of intermediate data subjected to preprocessing by subtraction, respectively. The product sum operation unit includes a data rearranging unit for outputting, in parallel and in order, bit data of the same figure of a set of data, a partial sum generator for generating a partial sum by using the parallel bit data as an address, and an accumulator for accumulating outputs of the partial sum generator. A one-dimensional inverse discrete cosine transform processor of N-term input data X includes a unit for performing a product sum operation of input data, and a postprocessing section for carrying out addition and subtraction of 2-term data in a predetermined combination of an output of the product sum operation unit. The number of times of multiplication is reduced by utilizing inherent characteristics of coefficients of DCT/IDCT processing. Since the product sum operation is performed by a ROM table and an adder, a faster multiplication is realized.

公开(公告)号：US06320909B1

公开(公告)日：2001-11-20

申请号：US09567010

申请日：2000-05-09

申请人： Akihiko Takabatake ,  Shinichi Uramoto

发明人： Akihiko Takabatake ,  Shinichi Uramoto

IPC分类号： H04N712

CPC分类号： H04N19/427 ,  H04N19/423 ,  H04N19/61

摘要： A memory having a storage capacity of storing pixel data of one frame is employed as a bank for display of bidirectional predictive encoded pixel data, and time difference between a timing for starting decoding of a given frame in a decoding unit and that for starting display of pixel data of the given frame in a display unit is set at one field time. The storage capacity of a memory device employed for display of pixel data is reduced in a picture decoding and display unit having a decoding and display function.

摘要翻译： 具有存储一个帧的像素数据的存储容量的存储器被用作用于显示双向预测编码像素数据的存储体，以及用于开始解码单元中给定帧的解码定时与开始显示之间的时间差 将显示单元中的给定帧的像素数据设置为一场时间。 在具有解码和显示功能的图像解码和显示单元中减少了用于显示像素数据的存储器件的存储容量。

公开(公告)号：US5185538A

公开(公告)日：1993-02-09

申请号：US710477

申请日：1991-06-05

申请人： Harufusa Kondoh ,  Shinichi Uramoto

发明人： Harufusa Kondoh ,  Shinichi Uramoto

IPC分类号： H03K19/0175 ,  G05F1/46 ,  G05F3/26 ,  G11C11/409 ,  H03K17/16

CPC分类号： H03K17/166 ,  G05F1/468 ,  G05F3/262

摘要： An output circuit is disclosed for a semiconductor integrated circuit, having a controllable load drive capability. In a training mode for setting a load drive capability, a comparator compares the output signal generated from a driver circuit with the externally designated reference voltage. The control circuit controls the load drive capability of the driver circuit in response to the result of the comparison. The load drive capability of driver circuit 2 is set to a desired value by repeating the processing for these comparison and control. Accordingly, by externally controlling the level of the reference voltage, an output buffer can be obtained which is capable of setting the load drive capability to any value.

摘要翻译： 公开了一种具有可控负载驱动能力的半导体集成电路的输出电路。 在用于设置负载驱动能力的训练模式中，比较器将从驱动器电路产生的输出信号与外部指定的参考电压进行比较。 响应于比较结果，控制电路控制驱动电路的负载驱动能力。 驱动电路2的负载驱动能力通过重复这些比较和控制的处理而被设定为期望值。 因此，通过外部控制参考电压的电平，可以获得能够将负载驱动能力设定为任何值的输出缓冲器。

公开(公告)号：US5850483A

公开(公告)日：1998-12-15

申请号：US780369

申请日：1997-01-09

申请人： Akihiko Takabatake ,  Shinichi Uramoto ,  Takashi Hashimoto

发明人： Akihiko Takabatake ,  Shinichi Uramoto ,  Takashi Hashimoto

IPC分类号： H04N5/907 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06T9/00 ,  G09G5/393 ,  G11C11/401 ,  G11C11/407 ,  H04N9/804 ,  H04N9/808 ,  H04N11/04 ,  H04N19/00 ,  H04N19/423 ,  H04N19/44 ,  H04N19/46 ,  H04N19/503 ,  H04N19/523 ,  H04N19/57 ,  H04N19/70 ,  G06K9/36 ,  G06K9/46

CPC分类号： H04N19/00 ,  G09G5/393 ,  H04N19/423 ,  H04N19/61 ,  H04N11/04 ,  H04N5/4401 ,  H04N5/907

摘要： A synchronous semiconductor memory device is utilized as an image data storage memory, and at most two pixels as one word are alternately stored in first and second banks of the synchronous semiconductor memory device. Respective pixel data of two types of color-difference signals as to the same pixel are stored in the same address position of the banks of the synchronous semiconductor memory device. Necessary data can be transferred by the burst length of the synchronous semiconductor memory device while suppressing overhead of page change to the minimum by alternately accessing the first and second banks.

摘要翻译： 使用同步半导体存储器件作为图像数据存储存储器，并且至少两个像素作为一个字交替存储在同步半导体存储器件的第一和第二存储体中。 相同像素的两种色差信号的各像素数据被存储在同步半导体存储器件的存储体的相同地址位置。 通过交替访问第一和第二存储体，可以通过同步半导体存储器件的突发长度传送所需的数据，同时将页面改变的开销抑制到最小。

公开(公告)号：US5233233A

公开(公告)日：1993-08-03

申请号：US781611

申请日：1991-10-23

申请人： Yoshitsugu Inoue ,  Shinichi Uramoto ,  Shinichi Nakagawa

发明人： Yoshitsugu Inoue ,  Shinichi Uramoto ,  Shinichi Nakagawa

IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/507 ,  G06F7/508 ,  H03K17/00 ,  H03K17/693

CPC分类号： G06F7/503 ,  H03K17/693 ,  G06F2207/4812

摘要： The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and transferring a second logic signal to the output node. The first and second gates turn on complementarily to each other. The first gate has an output load capacitance viewed from the output node less than that of the second gate. The first gate receives, as the first logic signal, a signal not required to be transmitted at a high speed, or a signal of a predetermined logic level or a fixed level. The second gate receives, as the second signal, a signal to be transmitted at a high speed. Since the second gate has a less output load capacitance, the second gate is allowed to transmit a signal at a high speed.

摘要翻译： 半导体集成电路器件包括用于选择性地发送信号的选择栅极。 选择门包括用于接收并将第一逻辑信号传送到输出节点的第一门和用于接收第二逻辑信号并将其传送到输出节点的第二门。 第一和第二个门互补互补。 第一栅极具有从输出节点观察到的小于第二栅极的输出负载电容。 第一栅极作为第一逻辑信号接收不需要高速传输的信号，或预定逻辑电平或固定电平的信号。 第二栅极作为第二信号接收要高速传输的信号。 由于第二栅极具有较小的输出负载电容，所以允许第二栅极以高速传输信号。

公开(公告)号：US5068818A

公开(公告)日：1991-11-26

申请号：US461966

申请日：1990-01-08

申请人： Shinichi Uramoto ,  Hideyuki Terane

发明人： Shinichi Uramoto ,  Hideyuki Terane

IPC分类号： G01R19/00 ,  G06F17/18 ,  H03H17/02

CPC分类号： G01R19/003 ,  G06F17/18 ,  H03H17/026

摘要： A device for finding a moving average of a signal applied from a signal source includes a first delay circuit for delaying input data sampled in a predetermined sampling period by a time period corresponding to N sampling periods where N is an integer, an accumulator for receiving an output of the first delay circuit and input data to store data of (N-1) terms, and a divider for dividing an output of the accumulator by a coefficient (N-1). The accumulator includes an adder, a second delay circuit for delaying an output of the adder by a time period corresponding to one sampling period, and a subtractor for carrying out subtraction between the output of the first delay circuit and that of the second delay circuit to supply a result of the subtraction to the divider. The adder adds input data and an output of the subtractor. This configuration enables implementation of the device for performing fast moving average processing with a simple configuration.

摘要翻译： 用于求出从信号源施加的信号的移动平均值的装置包括：第一延迟电路，用于将预定采样周期中采样的输入数据延迟一个对应于N为N的采样周期的时间段，N采样周期为N为整数， 输出第一延迟电路和输入数据以存储（N-1）项的数据，以及除法器，用于将累加器的输出除以系数（N-1）。 累加器包括加法器，用于将加法器的输出延迟与一个采样周期相对应的时间段的第二延迟电路，以及用于在第一延迟电路的输出与第二延迟电路的输出之间执行减法的减法器 将减法的结果提供给分频器。 加法器将输入数据和减法器的输出相加。 该配置使得能够以简单的配置实现用于执行快速移动平均处理的设备。

公开(公告)号：US5463340A

公开(公告)日：1995-10-31

申请号：US76649

申请日：1993-06-15

申请人： Akihiko Takabatake ,  Shinichi Uramoto ,  Shinichi Nakagawa

发明人： Akihiko Takabatake ,  Shinichi Uramoto ,  Shinichi Nakagawa

IPC分类号： G11C19/00 ,  G11C19/28 ,  H03K3/037 ,  H03K3/356

CPC分类号： H03K3/037 ,  G11C19/28 ,  H03K3/356156

摘要： A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

摘要翻译： 本发明的一般目的是提供一种需求量小的闩锁。 在半锁存器101中，在后期定时变化的控制信号T2和T2C被施加到用于数据输入（更新）操作的主单元，而在早期定时变化的控制信号T1和T1C被应用于用于数据保持的反馈单元 操作。 在数据保存操作完成之前，数据输入（更新）操作从不开始。 通过在由两个反相器构成的回路中保持具有负逻辑关系的两个信号来实现数据保持操作。 与数据延迟相关的信号和新输入的信号永远不在同一信号线上。 因此，避免了这些信号的碰撞，从而可以减少由于信号的碰撞引起的通电。