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公开(公告)号：US5652186A
公开(公告)日：1997-07-29
申请号：US632195
申请日：1996-04-15
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , H01L21/00
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。
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公开(公告)号：US08338247B2
公开(公告)日：2012-12-25
申请号：US12720174
申请日：2010-03-09
申请人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
发明人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823814 , H01L29/7843
摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。
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公开(公告)号：US08022445B2
公开(公告)日：2011-09-20
申请号：US12510026
申请日：2009-07-27
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7848
摘要： A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备具有平面方向为表面（100）的主表面的硅衬底; 形成具有栅电极，源极区，漏极区和沟道长度方向平行于硅衬底的晶体取向<100°的沟道的n沟道MISFET（金属绝缘体半导体场效应晶体管）; 并且在相同的步骤上在源极区域和漏极区域上在栅电极和NiSi 2上形成NiSi。
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公开(公告)号：US07936016B2
公开(公告)日：2011-05-03
申请号：US12413980
申请日：2009-03-30
IPC分类号： H01L29/76
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。
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公开(公告)号：US20100230761A1
公开(公告)日：2010-09-16
申请号：US12720174
申请日：2010-03-09
申请人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
发明人： Tadashi Yamaguchi , Toshiaki Tsutsumi , Satoshi Ogino , Kazumasa Yonekura , Kenji Kawai , Yoshihiro Miyagawa , Tomonori Okudaira , Keiichiro Kashihara , Kotaro Kihara
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823807 , H01L21/823814 , H01L29/7843
摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.
摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。
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公开(公告)号：US20090079007A1
公开(公告)日：2009-03-26
申请号：US12211925
申请日：2008-09-17
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L29/045 , H01L21/823807 , H01L27/105 , H01L27/11 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) which are formed over a semiconductor substrate having a main surface with a (110) plane orientation and have a source region and a drain region at least one of which has thereover nickel silicide or a nickel alloy silicide. Of these NMISFETs, those having a channel width less than 400 nm are laid out so that their channel length direction is parallel to a crystal orientation.
摘要翻译： 本发明可以防止在Si（110）衬底上形成的具有硅化源极/漏极区域的NMISFET中产生漏电流。 半导体器件包括N沟道MISFET（金属绝缘体半导体场效应晶体管），其形成在具有（110）面取向的主表面的半导体衬底上，并且具有源极区和漏极区，其中至少一个具有镍 硅化物或镍合金硅化物。 在这些NMISFET中，沟道宽度小于400nm的那些被布置成使得它们的沟道长度方向平行于<100>晶体取向。
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公开(公告)号：US20070284671A1
公开(公告)日：2007-12-13
申请号：US11759564
申请日：2007-06-07
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/823871 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/66545
摘要： Gate electrodes made of polysilicon film are isolated and face each other by way of a side wall spacer portion that fills a gap formed above an isolation insulating film at the boundary of NMIS region and PMIS region. A first metal film is formed on one of the gate electrodes, and an inhomogeneous second metal film is formed on the other of the gate electrodes. The both gate electrodes become inhomogeneous metal silicide gates through the promotion of silicide reaction by heat treatment. The mutual diffusion of metal atoms from the metal film to the gate electrode is suppressed by the interposition of the side wall spacer portion being an insulating film.
摘要翻译： 由多晶硅膜制成的栅电极被隔离并且通过填充在NMIS区域和PMIS区域的边界处的隔离绝缘膜上形成的间隙的侧壁间隔部分相互面对。 在一个栅电极上形成第一金属膜，另一个栅电极上形成非均匀的第二金属膜。 通过热处理促进硅化物反应，两个栅电极成为不均匀的金属硅化物栅极。 通过插入作为绝缘膜的侧壁间隔物部分来抑制金属膜从金属膜到栅电极的相互扩散。
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18.发明授权公开(公告)号：US06278150B1
公开(公告)日：2001-08-21
申请号：US08804530
申请日：1997-02-21
IPC分类号： H01L27108
CPC分类号： H01L21/76856 , H01L21/76841 , H01L21/76843 , H01L21/7685 , H01L27/10882 , H01L27/10894 , H01L2221/1078
摘要： A conductive layer connecting structure has a barrier layer preventing mutual diffusion between silicon and platinum group elements even when they are heated to a high temperature. The conductive layer connecting structure includes a plug containing doped polycrystalline silicon, a barrier layer formed on the plug and containing titanium, silicon and nitrogen, and a lower electrode layer formed on the barrier layer and containing platinum.
摘要翻译： 导电层连接结构具有防止硅和铂族元素之间的相互扩散的阻挡层，即使它们被加热到高温。 导电层连接结构包括含有掺杂多晶硅的插塞，形成在插塞上并包含钛，硅和氮的阻挡层，以及形成在阻挡层上并含有铂的下电极层。
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公开(公告)号：US08343827B2
公开(公告)日：2013-01-01
申请号：US13182750
申请日：2011-07-14
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.
摘要翻译： 在CMIS器件中，为了改善通过使用应变硅技术形成的n沟道电场晶体管的工作特性，而不降低p沟道场效应晶体管的工作特性。 在形成pISIS的nMIS和源极/漏极（p型延伸区域和p型扩散区域）的源极/漏极（n型延伸区域和n型扩散区域）之后， 源极/漏极具有所需的浓度分布和电阻，在n型扩散区域中形成具有所需量的应变的Si：C层，因此Si：C层中的最佳寄生电阻和最佳应变量 在nMIS的源/漏中获得。 此外，通过在等于或短于1毫秒的短时间内形成Si：C层进行热处理，已经形成的p型延伸区域的各个p型杂质的浓度分布的变化和 p型扩散区被抑制。
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20.发明申请METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CARRYING OUT ION IMPLANTATION BEFORE SILICIDE PROCESS 有权制造半导体器件的方法在硅化工艺之前进行离子植入公开(公告)号：US20100171183A1
公开(公告)日：2010-07-08
申请号：US12727334
申请日：2010-03-19
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。
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