公开(公告)号：US20060087117A1

公开(公告)日：2006-04-27

申请号：US11301535

申请日：2005-12-13

申请人： Hidesaburo Ishii ,  Kazuo Yano

发明人： Hidesaburo Ishii ,  Kazuo Yano

IPC分类号： F16L13/00

CPC分类号： F16L37/00 ,  F16L55/041 ,  F16L2201/00

摘要： A tube fitting capable of absorbing vibration and shock resulting from a high pressure fluid passing through the tube fitting while it is used includes a connection head, a connection nipple, and an intermediate connection member. The connection head and the connection nipple are provided with an annular collar projecting from an end surface of the connection head and the connection nipple. The connection head, the connection nipple and the intermediate connection member are joined by inserting the annular collars into both ends of the intermediate connection member.

公开(公告)号：US07009243B2

公开(公告)日：2006-03-07

申请号：US10985946

申请日：2004-11-12

申请人： Tomoyuki Ishii ,  Kazuo Yano

发明人： Tomoyuki Ishii ,  Kazuo Yano

IPC分类号： H01L29/788

CPC分类号： G11C11/405 ,  G11C11/404 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156

摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

公开(公告)号：US06970017B2

公开(公告)日：2005-11-29

申请号：US09946440

申请日：2001-09-06

申请人： Yohei Akita ,  Naoki Kato ,  Kazuo Yano

发明人： Yohei Akita ,  Naoki Kato ,  Kazuo Yano

IPC分类号： H03K3/356 ,  H03K3/3562 ,  H03K17/693 ,  H03K19/094

CPC分类号： H03K3/356156 ,  H03K3/35625 ,  H03K17/693

摘要： There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function.A logic circuit having the circuitry shown in FIG. 6 will be described briefly. Two transmission gates TG10a (TG10b) and TG11 and two inverters IV10 and IV11 are used to define a data propagation path from an input port I1 (I2) to an output port O1. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG10a (TG10b) is controlled using a NOR circuit 12a that inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuit 12b that inputs the clock CLK and the select signal sel). The transmission gate TG11 is controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output.When a D flip-flop circuit with a data-selecting function that causes the same delay time as a conventional D flip-flop circuit is adapted to a pipeline circuit, the action of the pipeline circuit can be speeded up.

摘要翻译： 提供了与常规逻辑电路相同的延迟时间并用作具有数据选择功能的D触发器电路的逻辑电路。 具有图1所示电路的逻辑电路。 将简要描述图6。 使用两个传输门TG10a（TG10b）和TG11以及两个反相器IV10和IV11来定义从输入端口I 1（I 2）到输出端口O 1的数据传播路径。 因此，沿着路径以与常规D触发器电路中相同的方式定位四个逻辑门。 传输门TG10a（TG10b）使用输入时钟CLK和与选择信号sel相反的选择信号/ sel（输入时钟CLK的NOR电路12b）的NOR电路12a和 选择信号sel）。 传输门TG11由时钟CLK控制。 基于选择信号选择两个输入数据项之一，然后输出。 当具有导致与常规D触发器电路相同的延迟时间的数据选择功能的D触发器电路适用于流水线电路时，可以加速流水线电路的动作。

公开(公告)号：US20050087797A1

公开(公告)日：2005-04-28

申请号：US10985946

申请日：2004-11-12

申请人： Tomoyuki Ishii ,  Kazuo Yano

发明人： Tomoyuki Ishii ,  Kazuo Yano

IPC分类号： H01L27/10 ,  B82B1/00 ,  G11C11/404 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C11/405 ,  G11C11/404 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156

摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

摘要翻译： 半导体存储器件包括：第一晶体管，包括源极区，漏极区，形成在绝缘膜上并连接源极区和漏极区的半导体材料的第一沟道区;以及栅电极，用于控制第一 渠道区域 第二晶体管，包括源极区域，漏极区域，连接源极区域和漏极区域的半导体材料的第二沟道区域，用于控制第二沟道区域的电位的第二栅电极和与第二沟道区域耦合的电荷存储区域 第二通道区域通过静电容量; 其中所述第二晶体管的源极区域连接到源极线，所述第一晶体管的源极或漏极区域的一端连接到所述第二晶体管的电荷存储区域，所述源极或漏极区域的另一端 的第一晶体管连接到数据线。

公开(公告)号：US06845349B1

公开(公告)日：2005-01-18

申请号：US09659735

申请日：2000-09-11

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06F17/50 ,  H03K19/173 ,  G06G7/62

CPC分类号： H03K19/1737 ,  G06F17/505 ,  H03K19/1736

摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

公开(公告)号：US06820242B2

公开(公告)日：2004-11-16

申请号：US10178216

申请日：2002-06-25

申请人： Shunzo Yamashita ,  Kazuo Yano

发明人： Shunzo Yamashita ,  Kazuo Yano

IPC分类号： G06F1750

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. A pass transistor selector operating as a NAND or NOR logic with any one of its two inputs, excluding the control input, being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value.

摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生具有优异特性（包括面积，延迟时间和功耗）的逻辑电路，从布尔函数创建二进制决策图。 各节点映射到2输入1输出1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 用作NAND或NOR逻辑的传输晶体管选择器被替换为操作为NAND或NOR逻辑的CMOS栅极，其两个输入中的任一个（不包括控制输入）被固定为逻辑常数“1”或“0” 如果通过替换获得的预定电路特性的值更接近于最佳值，则在逻辑上等效于通过晶体管选择器。

公开(公告)号：US06782499B2

公开(公告)日：2004-08-24

申请号：US10285573

申请日：2002-11-01

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

IPC分类号： G01R3128

CPC分类号： G11C29/028 ,  G11C15/00 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0403

摘要： A semiconductor integrated circuit device supplied as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing, more particularly to a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.

摘要翻译： 一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内置存储器的特性。 半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。 改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

公开(公告)号：US06646300B2

公开(公告)日：2003-11-11

申请号：US09811555

申请日：2001-03-20

申请人： Tomoyuki Ishii ,  Kazuo Yano

发明人： Tomoyuki Ishii ,  Kazuo Yano

IPC分类号： H01L29788

CPC分类号： G11C11/405 ,  G11C11/404 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156

摘要： A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

公开(公告)号：US06623210B2

公开(公告)日：2003-09-23

申请号：US10056042

申请日：2002-01-28

申请人： Yasuhiro Nomura ,  Kazuo Yano

发明人： Yasuhiro Nomura ,  Kazuo Yano

IPC分类号： E02B310

CPC分类号： E02B3/102 ,  Y02A10/12

摘要： A guidance system for protecting a specific zone as a safety zone against flood water while protecting landscapes near the specific zone from deteriorization. According to the described flood water guidance system, a guidance plate (5, 5, . . . ) is positioned under underground in the vicinity (S′1, S′2, S″1) of an upstream side of a specific zone (SI, S2) containing property to be protected and where it is anticipated that flood water will flow, and when flood water is generated, or when there is a possibility that flood water may be generated, the guidance plate (5, 5, . . . ) is raised to a predetermined height above the surface of the earth, in order that a specific zone (S1, S2) is protected as a safety zone by diverting the flood water from the specific zone (S1, S2) by way of the raised guidance plate (5, 5, . . . ), and by guiding the flood water to a retarding basin, a drainage canal, and the like.

摘要翻译： 保护特定区域作为防洪堤安全区的指导体系，同时保护特定区域附近的景观不会恶化。 根据所述的洪水引导系统，引导板（5,5 ...）位于特定区域的上游侧的附近（S'1，S'2，S'1）的下方 （SI，S2），包含要保护的物品，预计洪水将流动，并且当产生洪水时，或当可能产生洪水时，引导板（5，5，...） 通过将特定区域（S1，S2）通过将特定区域（S1，S2）的洪水从特定区域（S1，S2）分流而被保护作为安全区域，通过 升起的引导板（5,5 ...），并将洪水引导到延迟盆，排水管等。

公开(公告)号：US06514011B2

公开(公告)日：2003-02-04

申请号：US09742067

申请日：2000-12-22

申请人： Yasuhiro Nomura ,  Kazuo Yano

发明人： Yasuhiro Nomura ,  Kazuo Yano

IPC分类号： E02B740

CPC分类号： E02B3/104 ,  E06B9/00 ,  E06B2009/007 ,  F15B15/16

摘要： The present invention provides a movable water-protection apparatus capable of driving a water barrier plate manually or automatically when needed. The movable water-protection apparatus includes a water barrier plate (2, 50) for shutting out water, such as seawater, river water, and rainwater, likely to intrude into a basement (G) and a driving device for driving the water barrier plate (2, 50) upward from an underground position along a guide device (10) or a side plate (60). The water barrier plate (2, 50) is disposed in an underground space at an entrance of the basement (G). The driving device has a water pressure type piston/cylinder unit (20) to which service water is supplied.

摘要翻译： 本发明提供一种能够在需要时手动或自动地驱动防水板的可动防水装置。 可移动防水装置包括：用于关闭可能侵入基底（G）的海水，河水和雨水等水的防水板（2,50）和用于驱动防水板的驱动装置 （2,50）沿着引导装置（10）或侧板（60）从地下位置向上。 防水板（2,50）设置在地下室（G）的入口处的地下空间中。 驱动装置具有供水的水压式活塞/缸单元（20）。