利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

135 records (took 0.035 seconds)

    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110169070A1

    公开(公告)日：2011-07-14

    申请号：US13072211

    申请日：2011-03-25

    Applicant: Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    Inventor： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC: H01L27/088

    CPC classification number: H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    Abstract translation: 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US07009243B2

    公开(公告)日：2006-03-07

    申请号：US10985946

    申请日：2004-11-12

    Applicant: Tomoyuki Ishii ,  Kazuo Yano

    Inventor： Tomoyuki Ishii ,  Kazuo Yano

    IPC: H01L29/788

    CPC classification number: G11C11/405 ,  G11C11/404 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156

    Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

    Semiconductor memory device
    5.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20050087797A1

    公开(公告)日：2005-04-28

    申请号：US10985946

    申请日：2004-11-12

    Applicant: Tomoyuki Ishii ,  Kazuo Yano

    Inventor： Tomoyuki Ishii ,  Kazuo Yano

    IPC: H01L27/10 ,  B82B1/00 ,  G11C11/404 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788

    CPC classification number: G11C11/405 ,  G11C11/404 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156

    Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

    Abstract translation: 半导体存储器件包括：第一晶体管，包括源极区，漏极区，形成在绝缘膜上并连接源极区和漏极区的半导体材料的第一沟道区;以及栅电极，用于控制第一 渠道区域 第二晶体管，包括源极区域，漏极区域，连接源极区域和漏极区域的半导体材料的第二沟道区域，用于控制第二沟道区域的电位的第二栅电极和与第二沟道区域耦合的电荷存储区域 第二通道区域通过静电容量; 其中所述第二晶体管的源极区域连接到源极线，所述第一晶体管的源极或漏极区域的一端连接到所述第二晶体管的电荷存储区域，所述源极或漏极区域的另一端 的第一晶体管连接到数据线。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效

    公开(公告)号：US06646300B2

    公开(公告)日：2003-11-11

    申请号：US09811555

    申请日：2001-03-20

    Applicant: Tomoyuki Ishii ,  Kazuo Yano

    Inventor： Tomoyuki Ishii ,  Kazuo Yano

    IPC: H01L29788

    CPC classification number: G11C11/405 ,  G11C11/404 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156

    Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08278700B2

    公开(公告)日：2012-10-02

    申请号：US13072211

    申请日：2011-03-25

    Applicant: Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    Inventor： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC: H01L29/792

    CPC classification number: H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    Abstract translation: 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07939879B2

    公开(公告)日：2011-05-10

    申请号：US11896800

    申请日：2007-09-06

    Applicant: Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    Inventor： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC: H01L29/792

    CPC classification number: H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    Abstract translation: 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    Semiconductor memory device
    10.
    再颁专利
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：USRE41868E1

    公开(公告)日：2010-10-26

    申请号：US11708145

    申请日：2007-02-20

    Applicant: Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    Inventor： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC: H01L29/76 ,  H01L29/788

    CPC classification number: B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  H01L29/7889

    Abstract: A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

    Abstract translation: 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

Patent Agency Ranking