公开(公告)号：US07406643B2

公开(公告)日：2008-07-29

申请号：US10860051

申请日：2004-06-04

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

IPC分类号： G01R31/28 ,  G11C7/00

CPC分类号： G11C29/028 ,  G11C15/00 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0403

摘要： A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, an output register, a register controlled by a register control a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.

摘要翻译： 一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内部存储器的特性，制造器件的方法以及用于存储用于确定延迟次数的处理过程的介质 电路内置在用于设计的设备中。 半导体集成电路器件具有高速缓冲存储器，其包括由模式发生器，模式比较器，输出寄存器，由寄存器控制的寄存器控制寄存器写入信号组成的BIST电路; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。 改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

公开(公告)号：US06496952B1

公开(公告)日：2002-12-17

申请号：US09399330

申请日：1999-09-20

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

IPC分类号： G01R3128

CPC分类号： G11C29/028 ,  G11C15/00 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0403

摘要： A semiconductor integrated circuit device, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing are disclosed. More particularly, a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied is obtained. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by the BIST, thereby deciding the optimal timing.

摘要翻译： 公开了一种半导体集成电路器件，该器件的制造方法以及用于存储用于确定用于设计的器件中构建的延迟电路的数量的处理过程的介质。 更具体地说，即使在制造工艺条件变化的情况下，也能够确保写入和读出内置存储器的特性的半导体集成电路器件。 半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。 改变启用读出放大器的定时，并通过BIST测量存储器，从而确定最佳定时。

公开(公告)号：US06782499B2

公开(公告)日：2004-08-24

申请号：US10285573

申请日：2002-11-01

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Kazuo Yano ,  Tetsuro Honmura

IPC分类号： G01R3128

CPC分类号： G11C29/028 ,  G11C15/00 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0403

摘要： A semiconductor integrated circuit device supplied as an IP (Intellectual Property), etc., a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing, more particularly to a semiconductor integrated circuit device which guarantees the characteristics of writing into and reading from the built-in memory even when the manufacturing process conditions are varied. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, and an output register; a register controlled by a register control signal and a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.

摘要翻译： 一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内置存储器的特性。 半导体集成电路装置具有高速缓冲存储器，其包括由图案发生器，图案比较器和输出寄存器构成的BIST电路; 由寄存器控制信号和寄存器写入信号控制的寄存器; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。 改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

公开(公告)号：US07737509B2

公开(公告)日：2010-06-15

申请号：US12216716

申请日：2008-07-10

申请人： Koichiro Ishibashi ,  Kenichi Osada

发明人： Koichiro Ishibashi ,  Kenichi Osada

IPC分类号： H01L27/088

CPC分类号： G11C11/404 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/104 ,  H01L21/823807 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

摘要翻译： 在集成电路器件中，根据电路的特性，存在各种最佳栅极长度，栅极氧化物膜的厚度和阈值电压。 在其中电路集成在同一基板上的半导体集成电路器件中，制造过程复杂以便将电路设置为最佳值。 结果，伴随着产量的恶化和制造日数的增加，制造成本增加。 为了解决这些问题，根据本发明，在逻辑电路中使用高阈值和低阈值的晶体管，存储单元使用具有相同高阈值电压的晶体管和低阈值电压晶体管，以及输入/输出电路 使用在通道中具有相同高阈值电压和相同浓度的晶体管，以及较厚的栅极氧化物膜。

公开(公告)号：US20070133260A1

公开(公告)日：2007-06-14

申请号：US11657026

申请日：2007-01-24

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

公开(公告)号：US20060268647A1

公开(公告)日：2006-11-30

申请号：US11500339

申请日：2006-08-08

申请人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20060076610A1

公开(公告)日：2006-04-13

申请号：US11288287

申请日：2005-11-29

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L29/788

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US06998674B2

公开(公告)日：2006-02-14

申请号：US11104488

申请日：2005-04-13

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L29/788 ,  H01L21/8242

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

公开(公告)号：US20050146961A1

公开(公告)日：2005-07-07

申请号：US11042172

申请日：2005-01-26

申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC分类号： H01L27/10 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/02

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

摘要翻译： 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分为两部分，它们设置在N型阱区NW 1的相对侧，并形成为 形成晶体管的扩散层没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

公开(公告)号：US06795332B2

公开(公告)日：2004-09-21

申请号：US10163310

申请日：2002-06-07

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

IPC分类号： G11C1100

CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOB transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOB transistors is in-creased, the threshold voltage of the MOB transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOB transistor can be set to 1, thereby allowing a reduction in the memory cell area.

摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOB晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOB晶体管的电导被增加，所以可以减小存储单元内的MOB晶体管的阈值电压，而不会降低静态噪声容限。 此外，可以将驱动器MOS晶体管和转移MOB晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。