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    IrOx Nanostructure Electrode Neural Interface Optical Device
    12.
    发明申请
    IrOx Nanostructure Electrode Neural Interface Optical Device 有权
    IrOx纳米结构电极神经界面光学器件

    公开(公告)号：US20090024182A1

    公开(公告)日：2009-01-22

    申请号：US12240501

    申请日：2008-09-29

    申请人： Fengyan Zhang ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  Sheng Teng Hsu

    IPC分类号： A61N1/36

    CPC分类号： C30B25/00 ,  A61N1/0543 ,  B82Y5/00 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/904 ,  Y10S977/932

    摘要： An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

    摘要翻译： 提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。 该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。 具有第一电接口的光电器件连接到第一电极。 光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。 形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有电绝缘体，例如SiO 2，SiN，TiO 2或旋转玻璃（SOG），留下IrOx远端暴露。 在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

    Method of making CMOS devices on strained silicon on glass
    13.
    发明授权
    Method of making CMOS devices on strained silicon on glass 失效
    在玻璃上的应变硅上制造CMOS器件的方法

    公开(公告)号：US07470573B2

    公开(公告)日：2008-12-30

    申请号：US11060878

    申请日：2005-02-18

    申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Sheng Teng Hsu

    发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Yoshi Ono ,  Sheng Teng Hsu

    IPC分类号： H01L21/30 ,  H01L21/84

    CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/7842 ,  H01L29/78621

    摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

    摘要翻译： 在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

    Nanoelectrochemical cell
    14.
    发明授权
    Nanoelectrochemical cell 失效

    公开(公告)号：US07446014B2

    公开(公告)日：2008-11-04

    申请号：US11580623

    申请日：2006-10-12

    申请人： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： H01L21/20

    CPC分类号： H01G9/07 ,  Y10S977/762 ,  Y10T29/417

    摘要： A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.

    Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same
    16.
    发明申请
    Terbium-doped, silicon-rich oxide electroluminescent devices and method of making the same 有权
    铽掺杂，富硅氧化物电致发光器件及其制造方法

    公开(公告)号：US20080164569A1

    公开(公告)日：2008-07-10

    申请号：US11582275

    申请日：2006-10-16

    申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Teng Hsu

    IPC分类号： H01L29/00

    CPC分类号： H01L27/15 ,  H01L33/0004 ,  H01L33/343

    摘要： A method of fabricating an electroluminescent device includes, on a prepared substrate, depositing a rare earth-doped silicon-rich layer on gate oxide layer as a light emitting layer; and annealing and oxidizing the structure to repair any damage caused to the rare earth-doped silicon-rich layer; and incorporating the electroluminescent device into a CMOS IC. An electroluminescent device fabricated according to the method of the invention includes a substrate, a rare earth-doped silicon-rich layer formed on the gate oxide layer for emitting a light of a pre-determined wavelength; a top electrode formed on the rare earth-doped silicon-rich layer; and associated CMOS IC structures fabricated thereabout.

    摘要翻译： 一种制造电致发光器件的方法包括：在制备的衬底上，在作为发光层的栅极氧化物层上沉积稀土掺杂的富硅层; 并对该结构进行退火和氧化以修复对稀土掺杂的富硅层造成的任何损伤; 并将电致发光器件并入CMOS IC。 根据本发明的方法制造的电致发光器件包括：衬底，形成在栅极氧化物层上的用于发射预定波长的光的稀土掺杂富硅层; 在稀土掺杂的富硅层上形成的顶部电极; 并在其附近制造相关的CMOS IC结构。

    Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
    17.
    发明授权
    Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications 有权
    在应变硅CMOS应用中分离硅锗位错区的方法

    公开(公告)号：US07384837B2

    公开(公告)日：2008-06-10

    申请号：US11073185

    申请日：2005-03-03

    申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-shen Maa

    发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Douglas J. Tweet ,  Jer-shen Maa

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/78645

    摘要： A dual gate strained-Si MOSFET with thin SiGe dislocation regions and a method for fabricating the same are provided. The method forms a first layer of relaxed SiGe overlying a substrate, having a thickness of less than 5000 Å; forms a second layer of relaxed SiGe overlying the substrate and adjacent to the first layer of SiGe, having a thickness of less than 5000 Å; forms a layer of strained-Si overlying the first and second SiGe layers; forms a shallow trench isolation region interposed between the first SiGe layer and the second SiGe layer; forms an p-well in the substrate and the overlying first layer of SiGe; forming forms a p-well in the substrate and the overlying second layer of SiGe; forms channel regions, in the strained-Si, and forms PMOS and NMOS transistor source and drain regions.

    摘要翻译： 提供具有薄SiGe位错区域的双栅应变Si MOSFET及其制造方法。 该方法形成覆盖衬底的第一层松弛SiGe，厚度小于5000; 形成覆盖衬底并且邻近第一SiGe层的第二层松弛SiGe，其厚度小于5000; 形成层叠在第一和第二SiGe层上的应变层; 形成介于第一SiGe层和第二SiGe层之间的浅沟槽隔离区; 在衬底和SiGe的上覆第一层中形成p阱; 在衬底和SiGe的上覆第二层中形成p阱; 在应变Si中形成沟道区，并形成PMOS和NMOS晶体管的源极和漏极区。

    Method of fabricating local interconnects on a silicon-germanium 3D CMOS
    18.
    发明授权
    Method of fabricating local interconnects on a silicon-germanium 3D CMOS 有权
    在硅 - 锗3D CMOS上制造局部互连的方法

    公开(公告)号：US07378309B2

    公开(公告)日：2008-05-27

    申请号：US11376542

    申请日：2006-03-15

    申请人： Jong-Jan Lee ,  Paul J. Schuele ,  Sheng Teng Hsu ,  Jer-Shen Maa

    发明人： Jong-Jan Lee ,  Paul J. Schuele ,  Sheng Teng Hsu ,  Jer-Shen Maa

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823871 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/28525 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1108

    摘要： A method of fabricating local interconnect on a silicon-germanium 3D CMOS includes fabricating an active silicon CMOS device on a silicon substrate. An insulator layer is deposited on the silicon substrate and a seed window is opened through the insulator layer to the silicon substrate and to a silicon CMOS device gate. A germanium thin film is deposited on the insulator layer and into windows, forming a contact between the germanium thin film and the silicon device. The germanium thin film is encapsulated in a dielectric material. The wafer is heated at a temperature sufficient to flow the germanium, while maintaining the other layers in a solid condition. The wafer is cooled to solidify the germanium as single crystal germanium and as polycrystalline germanium, which provides local interconnects. Germanium CMOS devices may be fabricated on the single crystal germanium thin film.

    摘要翻译： 在硅 - 锗3D CMOS上制造局部互连的方法包括在硅衬底上制造有源硅CMOS器件。 绝缘体层沉积在硅衬底上，并且晶种窗通过绝缘体层向硅衬底和硅CMOS器件栅极打开。 在绝缘体层和窗口上沉积锗薄膜，形成锗薄膜和硅器件之间的接触。 锗薄膜被封装在电介质材料中。 在足以使锗流动的温度下加热晶片，同时将其它层保持在固体状态。 将晶片冷却以将锗固化为单晶锗和作为多晶锗，其提供局部互连。 可以在单晶锗薄膜上制造锗CMOS器件。

    Strain control of epitaxial oxide films using virtual substrates
    19.
    发明授权
    Strain control of epitaxial oxide films using virtual substrates 有权
    使用虚拟衬底的外延氧化膜的应变控制

    公开(公告)号：US07364989B2

    公开(公告)日：2008-04-29

    申请号：US11174350

    申请日：2005-07-01

    申请人： Douglas J. Tweet ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Douglas J. Tweet ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02192 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/3147

    摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

    摘要翻译： 一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

    Method of selective formation of compound semiconductor-on-silicon wafer with silicon nanowire buffer layer
    20.
    发明授权
    Method of selective formation of compound semiconductor-on-silicon wafer with silicon nanowire buffer layer 有权
    用硅纳米线缓冲层选择性形成硅化合物半导体晶片的方法

    公开(公告)号：US07358160B2

    公开(公告)日：2008-04-15

    申请号：US11481437

    申请日：2006-07-06

    申请人： Tingkai Li ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Sheng Teng Hsu

    IPC分类号： H01L21/36

    CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02538 ,  H01L21/7624

    摘要： A compound semiconductor-on-silicon (Si) wafer with a Si nanowire buffer layer is provided, along with a corresponding fabrication method. The method forms a Si substrate. An insulator layer is formed overlying the Si substrate, with Si nanowires having exposed tips. Compound semiconductor is selectively deposited on the Si nanowire tips. A lateral epitaxial overgrowth (LEO) process grows compound semiconductor from the compound semiconductor-coated Si nanowire tips, to form a compound semiconductor layer overlying the insulator. Typically, the insulator layer overlying the Si substrate is a thermally soft insulator (TSI), silicon dioxide, or SiXNY, where X≦3 and Y≦4. The compound semiconductor can be GaN, GaAs, GaAlN, or SiC. In one aspect, the Si nanowire tips are carbonized, and SiC is selectively deposited overlying the carbonized Si nanowire tips, prior to the selective deposition of compound semiconductor on the Si nanowire tips.

    摘要翻译： 提供了具有Si纳米线缓冲层的化合物半导体硅（Si）晶片以及相应的制造方法。 该方法形成Si衬底。 在Si衬底上形成绝缘体层，Si纳米线具有暴露的尖端。 化合物半导体选择性沉积在Si纳米线尖端上。 横向外延生长（LEO）工艺从化合物半导体涂覆的Si纳米线尖端生长化合物半导体，以形成覆盖绝缘体的化合物半导体层。 通常，覆盖Si衬底的绝缘体层是热软绝缘体（TSI），二氧化硅或Si X N Y ，其中 X <= 3 AND Y <= 4。 化合物半导体可以是GaN，GaAs，GaAlN或SiC。 在一个方面，将Si纳米线尖端碳化，并且在Si纳米线尖端上选择性沉积化合物半导体之前，选择性地将SiC沉积在碳化Si纳米线尖端上。