公开(公告)号：US08190599B2

公开(公告)日：2012-05-29

申请号：US12631255

申请日：2009-12-04

申请人： Naohiro Suzuki ,  Naoki Ikawa

发明人： Naohiro Suzuki ,  Naoki Ikawa

IPC分类号： G06F7/00

CPC分类号： G06F17/30463

摘要： An operation management program collects a query status table of a migration-source agent processing program and creates a server status table. The operation management program, based on the server status table, computes a migration cost for each query, and selects the query with the smallest migration cost as a migration query. Then, the operation management program migrates the selected query, using the optimum migration method.

摘要翻译： 操作管理程序收集迁移源代理处理程序的查询状态表，并创建服务器状态表。 操作管理程序根据服务器状态表计算每个查询的迁移成本，并选择迁移成本最小的查询作为迁移查询。 然后，运行管理程序使用最佳迁移方法迁移所选查询。

公开(公告)号：US07745276B2

公开(公告)日：2010-06-29

申请号：US12068263

申请日：2008-02-05

申请人： Eiichi Okuno ,  Hiroki Nakamura ,  Naohiro Suzuki

发明人： Eiichi Okuno ,  Hiroki Nakamura ,  Naohiro Suzuki

IPC分类号： H01L21/8234

CPC分类号： H01L29/7828 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer.

摘要翻译： 一种制造SiC半导体器件的方法包括：制备具有（11-20）取向表面的SiC衬底; 在衬底上形成漂移层; 在漂移层中形成基极区; 在所述基底区域中形成第一导电类型区域; 在所述基极区上形成沟道区，以在所述漂移层和所述第一导电类型区之间耦合; 在沟道区上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 形成电连接到所述第一导电类型区域的第一电极; 以及在所述衬底的背面上形成第二电极。 该器件通过控制沟道区域来控制第一和第二电极之间的电流。 形成基极区域包括外延地形成漂移层上的基极区域的下部。

公开(公告)号：US20090166730A1

公开(公告)日：2009-07-02

申请号：US12318183

申请日：2008-12-23

申请人： Eiichi Okuno ,  Naohiro Suzuki ,  Nobuyuki Kato

发明人： Eiichi Okuno ,  Naohiro Suzuki ,  Nobuyuki Kato

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate; a drift layer on the substrate; a trench on the drift layer; a base region in the drift layer sandwiching the trench; a channel between the base region and the trench; a source region in the base region sandwiching the trench via the channel; a gate electrode in the trench via a gate insulation film; a source electrode coupled with the source region; a drain electrode on the substrate opposite to the drift layer; and a bottom layer under the trench. An edge portion of the bottom layer under a corner of a bottom of the trench is deeper than a center portion of the bottom layer under a center portion of the bottom of the trench.

摘要翻译： SiC半导体器件包括：衬底; 衬底上的漂移层; 漂移层上的沟槽; 夹在沟槽中的漂移层中的基底区域; 基极区域和沟槽之间的沟道; 所述基极区域中的源极区域经由所述沟道夹持所述沟槽; 通过栅极绝缘膜在沟槽中的栅电极; 与源极区域耦合的源电极; 衬底上的与漂移层相反的漏电极; 和沟槽下方的底层。 在沟槽的底部的角部下方的底层的边缘部分比沟槽底部的中心部分下方的底层的中心部分更深。

公开(公告)号：US07825449B2

公开(公告)日：2010-11-02

申请号：US12289624

申请日：2008-10-30

申请人： Naohiro Suzuki ,  Yuuichi Takeuchi ,  Takeshi Endo ,  Eiichi Okuno ,  Toshimasa Yamamoto

发明人： Naohiro Suzuki ,  Yuuichi Takeuchi ,  Takeshi Endo ,  Eiichi Okuno ,  Toshimasa Yamamoto

IPC分类号： H01L29/94 ,  H01L21/04 ,  H01L29/68

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7397 ,  H01L29/7828

摘要： An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p+-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p+-type deep layer and an n−-type drift layer to extend into the n−-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.

摘要翻译： 公开了一种SiC半导体器件和相关制造方法，其具有设置有等于或大于沟槽深度形成的p +型深层的结构，以在p +型之间的PN结处引起耗尽层 深层和n型漂移层以非常长的长度延伸到n型漂移层中，使得由于漏极电压引起的不利影响导致的高电压难以进入栅极氧化膜 。 这导致使栅极氧化膜中的电场浓度最小化的能力，即在沟槽的底壁处的栅极氧化膜处发生的电场浓度。

公开(公告)号：US07679143B2

公开(公告)日：2010-03-16

申请号：US11415228

申请日：2006-05-02

申请人： Naohiro Suzuki ,  Hitoshi Yamaguchi

发明人： Naohiro Suzuki ,  Hitoshi Yamaguchi

IPC分类号： H01L23/62

CPC分类号： H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/7818 ,  H01L29/7825 ,  H01L29/7835

摘要： A semiconductor device includes: a MOS transistor; a protection diode; and a semiconductor substrate. The MOS transistor and the protection diode are disposed in the semiconductor substrate. The drain of the MOS transistor is connected to the cathode of the protection diode. The source of the MOS transistor is connected to the anode of the protection diode. The MOS transistor has a withstand voltage defined as VT. The protection diode has a withstand voltage defined as VD, a parasitic resistance defined as RD, and a maximum current defined as IRmax. They satisfy a relationship of VT>VD+IRmax×RD. The maximum current of IRmax is equal to or larger than 45 Amperes.

摘要翻译： 半导体器件包括：MOS晶体管; 保护二极管; 和半导体衬底。 MOS晶体管和保护二极管设置在半导体衬底中。 MOS晶体管的漏极连接到保护二极管的阴极。 MOS晶体管的源极连接到保护二极管的阳极。 MOS晶体管具有定义为VT的耐受电压。 保护二极管具有定义为VD的耐受电压，定义为RD的寄生电阻和定义为IRmax的最大电流。 它们满足VT> VD + IRmax×RD的关系。 IRmax的最大电流等于或大于45安培。

公开(公告)号：US07553722B2

公开(公告)日：2009-06-30

申请号：US11434124

申请日：2006-05-16

申请人： Jun Sakakibara ,  Hitoshi Yamaguchi ,  Naohiro Suzuki

发明人： Jun Sakakibara ,  Hitoshi Yamaguchi ,  Naohiro Suzuki

IPC分类号： H01L21/8242

CPC分类号： H01L29/861 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/7818

摘要： A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, wherein the substrate has a first conductive type; a first trench extending from the first surface of the semiconductor substrate in a depth direction; and an epitaxial semiconductor layer having a second conductive type, wherein the epitaxial semiconductor layer is disposed in the first trench. The first trench includes an inner wall as an interface between the semiconductor substrate and the epitaxial semiconductor layer so that the interface provides a PN junction. The first trench has an aspect ratio equal to or larger than 1.

摘要翻译： 半导体器件包括：具有第一表面和第二表面的半导体衬底，其中所述衬底具有第一导电类型; 在深度方向上从半导体衬底的第一表面延伸的第一沟槽; 以及具有第二导电类型的外延半导体层，其中所述外延半导体层设置在所述第一沟槽中。 第一沟槽包括作为半导体衬底和外延半导体层之间的界面的内壁，使得界面提供PN结。 第一沟槽具有等于或大于1的长宽比。

公开(公告)号：US20080230787A1

公开(公告)日：2008-09-25

申请号：US12076450

申请日：2008-03-19

申请人： Naohiro Suzuki ,  Tsuyoshi Yamamoto

发明人： Naohiro Suzuki ,  Tsuyoshi Yamamoto

IPC分类号： H01L31/0312 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7828

摘要： The silicon carbide semiconductor device includes a trench formed from a surface of a drift layer of a first conductivity type formed on a substrate of the first conductivity type, and a deep layer of a second conductivity type located at a position in the drift layer beneath the bottom portion of the trench. The deep layer is formed at a certain distance from base regions of the second conductivity type formed on the drift layer so as to have a width wider than the width of the bottom portion of the trench, and surround both the corner portions of the bottom portion of the trench.

摘要翻译： 碳化硅半导体器件包括由形成在第一导电类型的衬底上的第一导电类型的漂移层的表面形成的沟槽和位于漂移层中的位于第一导电类型的衬底下方的位置的第二导电类型的深层 沟槽的底部。 深层形成在与漂移层上形成的第二导电类型的基极区相距一定距离处，以使其宽度大于沟槽底部的宽度，并且包围底部的两个角部 的沟槽。

公开(公告)号：US06972458B2

公开(公告)日：2005-12-06

申请号：US10729955

申请日：2003-12-09

申请人： Naohiro Suzuki ,  Jun Sakakibara ,  Yoshitaka Noda ,  Hitoshi Yamaguchi

发明人： Naohiro Suzuki ,  Jun Sakakibara ,  Yoshitaka Noda ,  Hitoshi Yamaguchi

IPC分类号： H01L29/41 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8248 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/732 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66681 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/7825

摘要： A semiconductor device includes a base P region, a source N+ region, and a drain N+ region formed in a surface layer portion on a principal surface in an N− silicon layer. In the surface layer portion on the principal surface, an N well region is formed deeper than the drain N+ region in a region including the drain N+ region and is in contact with the base P region. A trench is formed so as to penetrate the base P region in a direction toward the drain N+ region from the source N+ region as a planar structure. A gate electrode is formed via a gate insulating film in the inside of the trench.

摘要翻译： 半导体器件包括在N - 硅层。 在主表面的表层部分，在包括漏极N + SUP区域的区域中，N阱区形成得比漏极N + + SUP区域深，并与之接触 与基地区P。 形成沟槽，以从源极N +区域的漏极N + SUP区域的方向穿过基极P区域作为平面结构。 栅极电极通过沟槽内部的栅极绝缘膜形成。

公开(公告)号：US09674058B2

公开(公告)日：2017-06-06

申请号：US14351824

申请日：2011-11-07

申请人： Keita Shimasaki ,  Miyako Shimasaki ,  Naohiro Suzuki ,  Shuntaro Hitomi

发明人： Keita Shimasaki ,  Naohiro Suzuki ,  Shuntaro Hitomi

IPC分类号： H04L12/26 ,  G05B23/02 ,  G06F17/30 ,  G06Q10/10

CPC分类号： H04L43/0805 ,  G05B23/0221 ,  G06F17/30303 ,  G06F17/30424 ,  G06Q10/10 ,  H04L43/0852

摘要： A time series data processing device for processing time series data that is a sequence of data received from a system that is a processing target over time includes a time series data search processing unit that receives, for details of the time series data and occurrence time information, a time series data search condition including events of a plurality of the time series data and an interval condition that is a condition of time intervals of the events occurring, and changes the interval condition using an allowable time lag that is allowable time of a set time lag in a transmission source of the time series data to thereby reflect the set time lag in the time series data search condition; and a data monitoring unit that monitors the time series data received from the system that is the processing target, using the time series data search condition changed by the time series data search processing unit.

公开(公告)号：US08901573B2

公开(公告)日：2014-12-02

申请号：US14129998

申请日：2012-08-08

申请人： Yuichi Takeuchi ,  Naohiro Suzuki

发明人： Yuichi Takeuchi ,  Naohiro Suzuki

IPC分类号： H01L29/15 ,  H01L21/336 ,  H01L21/265 ,  H01L29/78 ,  H01L27/098 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/808 ,  H01L29/10

CPC分类号： H01L21/265 ,  H01L21/0465 ,  H01L27/098 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1025 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/78 ,  H01L29/8083

摘要： A semiconductor device includes a silicon carbide semiconductor substrate, a transistor formed in a cell region of the semiconductor substrate, and a voltage-breakdown-resistant structure formed in a region which surrounds an outer periphery of the cell region. The semiconductor substrate includes a first conductivity type substrate, a first conductivity type drift layer on the first conductivity type substrate, a second conductivity type layer on the drift layer, and a first conductivity type layer on the second conductivity type layer. The voltage-breakdown-resistant structure includes a first recess which surrounds the outer periphery of the cell region and reaches the drift layer, a trench located at a side surface of the recess on an inner periphery of the recess, and a second conductivity type buried layer buried in the trench to provide the side surface of the first recess.

摘要翻译： 半导体器件包括碳化硅半导体衬底，形成在半导体衬底的单元区域中的晶体管，以及形成在围绕电池区域的外周的区域中的耐电压击穿结构。 半导体衬底包括第一导电类型衬底，第一导电类型衬底上的第一导电类型漂移层，漂移层上的第二导电类型层和第二导电类型层上的第一导电类型层。 耐电压结构包括围绕电池区域的外周并到达漂移层的第一凹部，位于凹部的内周上的凹部的侧表面处的沟槽，以及第二导电类型埋置 埋置在沟槽中以提供第一凹部的侧表面。