公开(公告)号：US08234554B2

公开(公告)日：2012-07-31

申请号：US12170462

申请日：2008-07-10

申请人： Kerry Bernstein ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Norman J. Rohrer

IPC分类号： H03M13/00

CPC分类号： H03M13/15 ,  G06F11/1008 ,  H03M13/098 ,  H03M13/13 ,  H03M13/1505 ,  H03M13/19

摘要： An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.

摘要翻译： 在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位 处理器唤醒时出现软错误，例如作为上电顺序的一部分。

公开(公告)号：US20120066657A1

公开(公告)日：2012-03-15

申请号：US12880228

申请日：2010-09-13

申请人： Kerry Bernstein ,  James A. Culp ,  Leah M.P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  James A. Culp ,  Leah M.P. Pastel ,  Kirk D. Peterson ,  Norman J. Rohrer

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

摘要翻译： 披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。 根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。 或者，可以根据DFM修改建立集成电路的测试覆盖。 或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。 或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。 在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

公开(公告)号：US08097525B2

公开(公告)日：2012-01-17

申请号：US12201580

申请日：2008-08-29

申请人： John E. Barth, Jr. ,  Kerry Bernstein

发明人： John E. Barth, Jr. ,  Kerry Bernstein

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.

摘要翻译： 半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。 穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

公开(公告)号：US08013342B2

公开(公告)日：2011-09-06

申请号：US11939612

申请日：2007-11-14

申请人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： H01L29/04

CPC分类号： G06F17/5077 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/481 ,  H01L23/535 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/045 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01007 ,  H01L2924/01022 ,  H01L2924/00

摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US07996810B2

公开(公告)日：2011-08-09

申请号：US12103038

申请日：2008-04-15

申请人： Kerry Bernstein ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Norman J. Rohrer

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  H03K19/0016 ,  H03K19/0948

摘要： A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.

摘要翻译： 一种用于设计低泄漏单调CMOS逻辑电路的计算机系统。 执行计算机的系统实现以下步骤：（a）指定具有其阈值电压及其栅介质厚度的参考PFET和具有其阈值电压及其栅介质厚度的参考NFET; （b）用标准设计元件合成示意电路设计，标准设计元件包括一个或多个参考PFET和一个或多个参考NFET; （c）分析具有主要为高输入逻辑状态或主要为低输入逻辑状态的逻辑级的一个或多个电路; （d）选择确定为具有主要高输入逻辑状态或主要为低输入逻辑状态的一个或多个逻辑级; 和（e）用减少的电流泄漏元件代替所选逻辑级的标准设计元件。

公开(公告)号：US07960245B2

公开(公告)日：2011-06-14

申请号：US12029575

申请日：2008-02-12

申请人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

IPC分类号： H01L21/30

CPC分类号： H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

公开(公告)号：US07882334B2

公开(公告)日：2011-02-01

申请号：US11276236

申请日：2006-02-20

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F15/76 ,  G06F1/00

CPC分类号： G06F9/3869 ,  G11C27/026

摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

公开(公告)号：US07859878B2

公开(公告)日：2010-12-28

申请号：US12110375

申请日：2008-04-28

申请人： Igor Arsovski ,  Kerry Bernstein

发明人： Igor Arsovski ,  Kerry Bernstein

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括内容可寻址存储器（CAM）装置，其具有排列成字线方向的存储单元阵列和排列在位线方向上的列，并且配置有比较电路 将存储在阵列中的数据与存储在阵列的每一行和列中的数据进行比较，同时在阵列的每一行和列上指示匹配结果，从而产生二维的基于矩阵的数据比较操作。

公开(公告)号：US20100203689A1

公开(公告)日：2010-08-12

申请号：US12762427

申请日：2010-04-19

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US07692944B2

公开(公告)日：2010-04-06

申请号：US12127086

申请日：2008-05-27

申请人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

发明人： Kerry Bernstein ,  Paul W. Coteus ,  Philip G. Emma

IPC分类号： G11C5/02

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

摘要： An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

摘要翻译： 其制造的集成电路设计，结构和方法包括至少一个逻辑器件层和至少两个额外的分开的存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。