公开(公告)号：US20200303012A1

公开(公告)日：2020-09-24

申请号：US16799885

申请日：2020-02-25

申请人： Kioxia Corporation

发明人： Suguru NISHIKAWA ,  Riki SUZUKI ,  Yoshihisa KOJIMA

IPC分类号： G11C16/16 ,  G11C16/26 ,  G11C16/12 ,  G11C16/34 ,  G06F13/16

摘要： According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.

公开(公告)号：US20220358011A1

公开(公告)日：2022-11-10

申请号：US17869881

申请日：2022-07-21

申请人： Kioxia Corporation

发明人： Takehiko AMAKI ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

IPC分类号： G06F11/10 ,  G06F12/0891 ,  G06F12/02 ,  G06F11/07

摘要： According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.

公开(公告)号：US20220342606A1

公开(公告)日：2022-10-27

申请号：US17858294

申请日：2022-07-06

申请人： Kioxia Corporation

发明人： Suguru NISHIKAWA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI

IPC分类号： G06F3/06 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

摘要： A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.

公开(公告)号：US20220328102A1

公开(公告)日：2022-10-13

申请号：US17849062

申请日：2022-06-24

申请人： KIOXIA CORPORATION

发明人： Suguru NISHIKAWA ,  Yoshihisa KOJIMA ,  Riki SUZUKI ,  Masanobu SHIRAKAWA ,  Toshikatsu HIDA

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  G11C29/02 ,  G11C29/42 ,  G11C16/32

摘要： According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

公开(公告)号：US20220189561A1

公开(公告)日：2022-06-16

申请号：US17471569

申请日：2021-09-10

申请人： Kioxia Corporation

发明人： Tomoya KAMATA ,  Yoshihisa KOJIMA ,  Suguru NISHIKAWA

IPC分类号： G11C16/32 ,  G11C7/22

摘要： According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to cause the nonvolatile memory to execute a first process of reading data based on a first request from a host device. The memory controller is configured to, when the first request is received from the host device while causing the nonvolatile memory to execute a second process, hold interruption of the second process until a first number becomes a first threshold value or more. The first number is a number of the first requests to be performed in the memory controller. The first threshold value is an integer of 2 or more.