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11.发明授权High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage 失效高噪声边缘TTL缓冲电路能够在电源电压变化很大的情况下工作
公开(公告)号：US5612635A
公开(公告)日：1997-03-18
申请号：US408514
申请日：1995-03-22
申请人： Raghava Madhu , Subramani Kengeri
发明人： Raghava Madhu , Subramani Kengeri
IPC分类号： H03K3/3565 , H03K19/0185
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A buffer circuit for converting logic signals generated by apparatus implemented in a TTL technology to logic signals processed by apparatus implemented by the CMOS technology includes an input stage (10, 11, 12, 13, 17), a voltage-control (14, 15) stage for causing the buffer circuit to vary the input voltage level required to switch the state of the buffer circuit output signal, and a hysteresis stage (16) for causing the switching of the output signal level to be different for the rising and falling edges of the input signal. The voltage-control stage (14, 15) provides a improvement in the noise margin of both the VTTL(High) switching level and the VTTL(Low) switching level.
摘要翻译： 用于将由TTL技术实现的装置产生的逻辑信号转换成由CMOS技术实现的装置处理的逻辑信号的缓冲电路包括输入级（10,11,12,13,17），电压控制（14,15） ）级，用于使缓冲电路改变切换缓冲电路输出信号的状态所需的输入电压电平，以及用于使输出信号电平的切换对于上升沿和下降沿而不同的滞后级（16） 的输入信号。 电压控制级（14,15）提供VTTL（高）开关电平和VTTL（低）开关电平两者的噪声容限的改进。
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12.发明授权公开(公告)号：US08824226B2
公开(公告)日：2014-09-02
申请号：US12751542
申请日：2010-03-31
申请人： Ching-Hao Shaw , Subramani Kengeri
发明人： Ching-Hao Shaw , Subramani Kengeri
IPC分类号： G11C7/00 , G11C29/00 , G11C11/412 , H01L49/02 , H01L27/10 , H01L27/105 , H01L23/522
CPC分类号： G11C5/005 , G11C11/4125 , G11C11/417 , G11C29/52 , H01L23/5223 , H01L23/556 , H01L27/0629 , H01L27/101 , H01L27/105 , H01L27/1104 , H01L28/40 , H01L28/60 , H01L2924/0002 , Y10T29/43 , H01L2924/00
摘要： Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.
摘要翻译： 一些实施例涉及网状电容器，其提高了SER FIT速率。 在一个实施例中，电容器连接在触发器中的锁存器的输入和输出之间，使得触发器由于辐射（例如来自中子和/或α粒子）而更难翻转。 在一些实施例中，电容器直接垂直地构建在触发器的顶部，从而节省芯片布局区域。
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公开(公告)号：US20130146982A1
公开(公告)日：2013-06-13
申请号：US13324699
申请日：2011-12-13
申请人： Mahbub Rashed , Steven Soss , Jongwook Kye , Irene Y. Lin , James Benjamin Gullette , Chinh Nguyen , Jeff Kim , Marc Tarabbia , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , Steven Soss , Jongwook Kye , Irene Y. Lin , James Benjamin Gullette , Chinh Nguyen , Jeff Kim , Marc Tarabbia , Yuansheng Ma , Yunfei Deng , Rod Augur , Seung-Hyun Rhee , Scott Johnson , Subramani Kengeri , Suresh Venkatesan
IPC分类号： H01L27/088
CPC分类号： H01L21/76895 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.
摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 CA层电连接到第一晶体管的源极或漏极中的至少一个。 CB层电连接到晶体管和CA层的至少一个栅极。
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公开(公告)号：US08208329B2
公开(公告)日：2012-06-26
申请号：US13094389
申请日：2011-04-26
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C2207/104
摘要： A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.
摘要翻译： 一种操作存储电路的方法包括提供存储电路。 存储电路包括存储单元; 连接到存储单元的字线; 连接到存储单元的第一局部位线和第二局部位线; 以及分别耦合到第一和第二局部位线的第一全局位线和第二全局位线。 该方法还包括开始均衡以均衡第一和第二局部位线上的电压; 停止均衡 并且在开始均衡的步骤之后，在停止均衡的步骤之前，将值从第一和第二全局位线写入第一和第二局部位线。
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公开(公告)号：US07952946B2
公开(公告)日：2011-05-31
申请号：US12055095
申请日：2008-03-25
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C2207/104
摘要： A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.
摘要翻译： 一种操作存储电路的方法包括提供存储电路。 存储电路包括存储单元; 连接到存储单元的字线; 连接到存储单元的第一局部位线和第二局部位线; 以及分别耦合到第一和第二局部位线的第一全局位线和第二全局位线。 该方法还包括开始均衡以均衡第一和第二局部位线上的电压; 停止均衡 并且在开始均衡的步骤之后，在停止均衡的步骤之前，将值从第一和第二全局位线写入第一和第二局部位线。
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公开(公告)号：US07898875B2
公开(公告)日：2011-03-01
申请号：US12253735
申请日：2008-10-17
IPC分类号： G11C7/10
CPC分类号： G11C11/413
摘要： A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.
摘要翻译： 存储器电路包括存储器阵列，其还包括以行和列排列的多个存储单元; 多个第一位线，每个第一位线连接到存储器阵列的一列; 以及多个写入辅助锁存器，每个写入辅助锁存器连接到多个第一位线之一。 多个写入辅助锁存器中的每一个被配置为增加多个第一位线中的一个连接上的电压。
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17.发明授权公开(公告)号：US07606061B2
公开(公告)日：2009-10-20
申请号：US11835372
申请日：2007-08-07
申请人： Subramani Kengeri , Jhon-Jhy Liaw
发明人： Subramani Kengeri , Jhon-Jhy Liaw
CPC分类号： G11C11/412
摘要： An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit.
摘要翻译： SRAM装置包括：用于保留数据的锁存单元; 由字线控制的一个或多个传输门晶体管，用于将锁存单元耦合到位线和互补位线; 以及耦合到所述锁存单元的功率节省模块，用于响应于所述字线上的控制信号而提高所述锁存单元的源极电压，由此减小所述锁存单元的漏电流。
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公开(公告)号：US06434040B1
公开(公告)日：2002-08-13
申请号：US09793872
申请日：2001-02-23
申请人： Tae Hyoung Kim , Subramani Kengeri
发明人： Tae Hyoung Kim , Subramani Kengeri
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A static random access memory cell utilizes four NMOS transistors and does not require load elements. The semiconductor memory cell device maintains a stable data hold by utilizing a sub-threshold voltage to charge the word line, the sub-threshold voltage being higher than the low voltage reference of the memory cell device and lower than the threshold voltage of the NMOS access transistors. The sub-threshold voltage is biased to the word line during non-active and non-charging operations of the memory cell. The loadless four-transistor NMOS SRAM memory cell of the present invention requires a significantly smaller silicon area than prior art loadless four-transistor CMOS SRAM memory cells.
摘要翻译： 静态随机存取存储单元利用四个NMOS晶体管，不需要负载元件。 半导体存储单元器件通过利用子阈值电压对字线进行充电来保持稳定的数据保持，子阈值电压高于存储器单元器件的低电压基准并低于NMOS存取的阈值电压 晶体管。 在存储单元的非有源和非充电操作期间，子阈值电压被偏置到字线。本发明的无负载四晶体管NMOS SRAM存储单元需要比现有技术的无负载四通道SRAM存储单元小得多的硅面积， 晶体管CMOS SRAM存储单元。
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19.发明授权
公开(公告)号：US5872742A
公开(公告)日：1999-02-16
申请号：US63529
申请日：1998-04-21
CPC分类号： G11C7/1072 , G11C7/1039
摘要： A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).
摘要翻译： 公开了与外部时钟同步工作的静态随机存取存储器（SRAM）（10）。 同步SRAM（10）包括用于在外部时钟的上升沿之前的建立时间内解码外部地址的透明地址电路（14）。 定时和控制电路（18）与外部时钟的上升沿同步地产生字线使能（WLE）信号。 激活时，WLE激活字线驱动器（34），当不活动时，WLE均衡位线。 WLE被施加到第一延迟电路（60）以产生感测信号（SA）。 SA激活感测电路（46）并使WLE信号无效。 实现连续流水线访问，使得当地址被解码时，位线是均衡的，并且来自先前地址的数据通过数据I / O路径传播（16）。
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公开(公告)号：US5629646A
公开(公告)日：1997-05-13
申请号：US407568
申请日：1995-03-21
IPC分类号： G11C11/413 , G05F3/20 , G11C11/407 , H02M3/07 , G05F1/10
摘要： In a DRAM unit in which the substrate bias voltage is maintained within predetermined limits by a of voltage detectors and a charge pump, a third voltage detector is provided which detects a intermediate substrate bias voltage level that is within the voltage range identified by the pair of voltage detectors. When the third voltage level detects that the intermediate substrate bias voltage has been traversed, the charge pump is activated at a reduced level to drive the substrate bias voltage to recross the intermediate substrate bias voltage level. This technique permits the DRAM unit to operate in a stand-by mode at a lower power level, especially in a standby mode of operation, than when the substrate bias voltage is maintained only by the two voltage limit detectors and a single power level charge pump.
摘要翻译： 在其中通过电压检测器和电荷泵将衬底偏置电压保持在预定限度内的DRAM单元中，提供第三电压检测器，其检测在由该对电压检测器识别的电压范围内的中间衬底偏置电压电平 电压检测器 当第三电压电平检测到中间衬底偏置电压已经被移动时，电荷泵以降低的电平被激活，以驱动衬底偏置电压以跨越中间衬底偏置电压电平。 这种技术允许DRAM单元在较低功率电平下工作，特别是在待机操作模式下，与基板偏置电压仅由两个电压限制检测器和单个功率电平电荷泵 。
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