公开(公告)号：US20090321344A1

公开(公告)日：2009-12-31

申请号：US12486112

申请日：2009-06-17

Applicant: Kwang-Jin LEE ,  Moo-Seok LEE ,  Yong-Cheol SHIN

Inventor： Kwang-Jin LEE ,  Moo-Seok LEE ,  Yong-Cheol SHIN

IPC: B01D63/00 ,  B01D35/30

CPC classification number: B01D63/02 ,  B01D2313/21

Abstract: A header for filtering membrane module and a filtering membrane module using the same is disclosed, which is capable of maximizing efficiency in power consumption by securing a constant flow of permeate through the use of a relatively-low negative pressure, the header for filtering membrane module comprising a body with a permeate collecting space therein; and a conduit at one end of the body, the conduit being in fluid communication with the permeate collecting space, wherein at least a portion of the permeate collecting space has an inclined shape.

Abstract translation: 公开了用于过滤膜组件的头部和使用其的过滤膜组件，其能够通过使用相对低的负压确保渗透物的恒定流量来最大化功率消耗的效率，用于过滤膜组件 包括其中具有渗透物收集空间的主体; 以及在所述主体的一端处的导管，所述导管与所述渗透物收集空间流体连通，其中所述渗透物收集空间的至少一部分具有倾斜形状。

公开(公告)号：US20090161421A1

公开(公告)日：2009-06-25

申请号：US12395999

申请日：2009-03-02

Applicant: Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

Inventor： Woo-Yeong CHO ,  Kwang-Jin LEE ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C11/416

CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Abstract translation: 相变存储器件通过接收在所选择的存储器单元中被编程的程序数据来执行编程操作，当检验读取电压为检测电压时，通过检测流过选择的存储器单元的检验电流的大小来感测已经存储在所选存储单元中的读取数据 应用于所选择的存储单元，确定读取的数据是否与程序数据相同，并且在确定所选择的存储单元中的一个或多个的程序数据与相应的读取数据不相同时，编程所选择的一个或多个 存储单元与程序数据。

公开(公告)号：US20100103726A1

公开(公告)日：2010-04-29

申请号：US12652842

申请日：2010-01-06

Applicant: Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

Inventor： Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C7/02 ,  G11C5/14

CPC classification number: G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Abstract translation: 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US20090251954A1

公开(公告)日：2009-10-08

申请号：US12417679

申请日：2009-04-03

Applicant: Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

Inventor： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

IPC: G11C11/00 ,  G11C8/00 ,  G11C11/416

CPC classification number: G11C16/08 ,  G11C8/12

Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Abstract translation: 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

公开(公告)号：US20080159017A1

公开(公告)日：2008-07-03

申请号：US11955562

申请日：2007-12-13

Applicant: Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

Inventor： Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

IPC: G11C5/14

CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。