公开(公告)号：US20160072650A1

公开(公告)日：2016-03-10

申请号：US14479278

申请日：2014-09-06

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Sunil Srinivasa ,  Vladimir Sindalovsky ,  Amaresh V. Malipatil ,  Pervez M. Aziz

IPC: H04L25/06 ,  H04L7/00

CPC classification number: H04L25/06 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0278 ,  H04L25/0292

Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts termination impedance automatically to obtain a tuned termination. The termination adaptation is realized with a ‘biased’ bang-bang phase detector (BBPD) that biases the weights applied to UP and DOWN outputs of the phase detector. Through an optimization process, the system locks to data eye corners, and thereby is able to optimize termination though a predetermined criteria, such as signal to noise ratio (SNR), horizontal eye (H-) margin, vertical eye (V-) margin or joint SNR and H-/V-margin optimization. As part of the receiver equalization, adaptive termination tuning is performed after the SerDes receiver (RX) path is initially powered-up by tuning the termination above and below its current initial setting and performing the optimization process.

Abstract translation: 描述的实施例在SerDes设备中提供自适应调整终止阻抗以获得调谐终端的适配过程。 终端适配通过偏置的砰 - 相位相位检测器（BBPD）来实现，该相位检测器偏置施加到相位检测器的UP和DOWN输出的权重。 通过优化过程，系统锁定到数据眼角，从而能够通过诸如信噪比（SNR），水平眼（H）边缘，垂直眼（V-）边缘等预定标准来优化终止 或联合SNR和H / V边缘优化。 作为接收机均衡的一部分，在SerDes接收机（RX）路径最初上电之后，通过调谐高于和低于其当前初始设置的终止并执行优化过程来执行自适应终止调谐。

公开(公告)号：US20140269888A1

公开(公告)日：2014-09-18

申请号：US13803435

申请日：2013-03-14

Applicant: LSI CORPORATION

Inventor： Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H04L27/01

CPC classification number: H04L27/01 ,  H04L25/03057 ,  H04L25/03885

Abstract: An apparatus comprising an equalizer circuit, a converter circuit and an adaptation circuit. The equalizer circuit may be configured to generate an intermediate signal in response to an input signal and a gradient value. The converter circuit may be configured to generate a digital signal comprising a plurality of symbol values, including a main cursor symbol value, in response to the intermediate signal. The adaptation circuit may be configured to generate the gradient value in response to a plurality of the symbol values before the main cursor symbol value, a plurality of symbol values after the main cursor symbol value, and an error value.

Abstract translation: 一种包括均衡器电路，转换器电路和适配电路的装置。 均衡器电路可以被配置为响应于输入信号和梯度值而产生中间信号。 转换器电路可以被配置为响应于中间信号产生包括多个符号值的数字信号，包括主光标符号值。 适配电路可以被配置为响应于主光标符号值之前的多个符号值，主光标符号值之后的多个符号值和误差值来生成梯度值。

公开(公告)号：US09397674B2

公开(公告)日：2016-07-19

申请号：US14145493

申请日：2013-12-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Shiva Prasad Kotagiri ,  Sundeep Venkatraman ,  Sunil Srinivasa ,  Amaresh V. Malipatil

IPC: H03D3/24 ,  H03L7/087 ,  H03L7/06

CPC classification number: H03L7/087 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/093 ,  H04L7/0058 ,  H04L7/033

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract translation: 时钟和数据恢复装置包括相位检测器，量化器和环路滤波器。 相位检测器在表示相位调整时钟和输入数据信号之间的相位差的输出端产生相位误差采样。 量化器耦合到相位检测器的输出并响应于高阈值和低阈值，在输出端产生三值量化的相位误差样本。 环路滤波器对量化的相位误差样本或相位误差采样进行滤波，以控制相位控制时钟。 确定输入数据信号中存在的抖动频率的频率检测器寻址查找表以提供抖动频率相关的高和低阈值，并且控制环路滤波器处理哪些相位误差采样。 频率检测器通过取低通滤波相位误差样本的峰值比来确定抖动频率。

公开(公告)号：US20150195108A1

公开(公告)日：2015-07-09

申请号：US14146920

申请日：2014-01-03

Applicant: LSI Corporation

Inventor： Tomasz Prokop ,  Volodmyr Shvydun ,  Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H04L25/03 ,  H03M9/00 ,  G11C19/00

CPC classification number: H04L25/03057 ,  H03M9/00 ,  H04L2025/03535

Abstract: A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

Abstract translation: 一种使用串联耦合信号处理块来处理数字化输入符号的串行器 - 解串器，每个块具有系数输入。 多个串联耦合系数延迟元件中的每一个具有控制输入，并且耦合到对应的一个信号处理模块的系数输入的系数输出由具有输入和多个输出的移位寄存器控制，每个 所述多个输出耦合到所述系数延迟元件中对应的一个的所述控制输入。 适配单元具有耦合到移位寄存器的输入的标志输出，以及耦合到系数延迟元件中的第一个的输入的第一系数输出。 当自适应单元生成系数时，适配单元生成标志，并且当移位寄存器接收到标志时，该系数被输入到系数延迟元件中的第一个。

公开(公告)号：US08902959B2

公开(公告)日：2014-12-02

申请号：US13745363

申请日：2013-01-18

Applicant: LSI Corporation

Inventor： Viswanath Annampedu ,  Amaresh V. Malipatil ,  Adam B. Healey

IPC: H04B3/46 ,  H04L1/20 ,  H04B17/00

CPC classification number: H04L1/20 ,  H04B17/345

Abstract: The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver based on the normalized Nyquist energy.

Abstract translation: 本发明包括从建立在发射机和接收机之间的分散通信信道的输出接收信号，确定沿着在发射机和接收机之间建立的色散通信信道发送的信号的归一化奈奎斯特能量，并生成配置的映射表 以在基于归一化奈奎斯特能量的接收机接收的信号上识别在奈奎斯特频率处或接近奈奎斯特频率处的等于或高于所选公差电平的峰值。

公开(公告)号：US08860467B2

公开(公告)日：2014-10-14

申请号：US13866888

申请日：2013-04-19

Applicant: LSI Corporation

Inventor： Amaresh V. Malipatil ,  Sunil Srinivasa ,  Adam B. Healey ,  Pervez M. Aziz

IPC: G01R25/00 ,  H03L7/00

CPC classification number: H03L7/00 ,  H03L7/0807 ,  H03L7/089 ,  H03L7/091 ,  H04L7/033

Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Abstract translation: 一种装置包括多个相位检测器电路和一个求和电路。 多个相位检测器电路中的每一个可以被配置为响应于相应的数据样本对和中间转换样本而产生相位上升信号和相位降低信号。 求和电路可以被配置为响应于多个相位检测器电路的相位上升和下降信号而产生调整信号。 对相位相加信号和相位下降信号之和进行加权，以提供相位调整的偏置。

公开(公告)号：US20140266338A1

公开(公告)日：2014-09-18

申请号：US13866888

申请日：2013-04-19

Applicant: LSI Corporation

Inventor： Amaresh V. Malipatil ,  Sunil Srinivasa ,  Adam B. Healey ,  Pervez M. Aziz

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03L7/0807 ,  H03L7/089 ,  H03L7/091 ,  H04L7/033

Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Abstract translation: 一种装置包括多个相位检测器电路和一个求和电路。 多个相位检测器电路中的每一个可以被配置为响应于相应的数据样本对和中间转换样本而产生相位上升信号和相位降低信号。 求和电路可以被配置为响应于多个相位检测器电路的相位上升和下降信号而产生调整信号。 对相位相加信号和相位下降信号之和进行加权，以提供相位调整的偏置。

公开(公告)号：US20150349988A1

公开(公告)日：2015-12-03

申请号：US14291909

申请日：2014-05-30

Applicant: LSI Corporation

Inventor： Viswanath Annampedu ,  Amaresh V. Malipatil

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L2025/03503

Abstract: In one embodiment, an apparatus has an equalizer, a tap position locator, and a tap weight updater. The equalizer has a plurality of floating taps. The tap position locator generates metrics for a set of possible tap positions of the equalizer. Each possible tap position corresponds to a different tap weight, and the metrics are generated without updating the tap weights for all of the possible tap positions in the set. Further, the tap position locator selects a subset of possible tap positions from the set based on the metrics. The tap weight updater updates a subset of the tap weights corresponding to the selected subset of possible tap positions, and applies the updated subset of tap weights to the plurality of floating taps.

Abstract translation: 在一个实施例中，装置具有均衡器，抽头位置定位器和抽头重量更新器。 均衡器具有多个浮动抽头。 抽头位置定位器为均衡器的一组可能的抽头位置生成度量。 每个可能的分接位置对应于不同的抽头权重，并且生成度量而不更新集合中所有可能的抽头位置的抽头权重。 此外，抽头位置定位器基于度量从集合中选择可能的抽头位置的子集。 抽头重量更新器更新对应于所选择的可能抽头位置的子集的抽头权重的子集，并且将更新的抽头权重的子集应用于多个浮动抽头。

公开(公告)号：US09143367B2

公开(公告)日：2015-09-22

申请号：US13955676

申请日：2013-07-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Amaresh V. Malipatil ,  Viswanath Annampedu

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0029 ,  H04L7/02 ,  H04L7/033 ,  H04L2025/03598

Abstract: In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.

Abstract translation: 在所描述的实施例中，使用基于数字信号处理的SERDES装置来产生样本判定的方法包括：将模拟信号转换为数字信号，均衡数字信号，选择主CDR环路中的相位检测器的输入，计算相位差 信号，通过第一内插滤波器组产生对于最后均衡级的信号的相位偏移，产生控制信号以通过相位偏移适配环路来控制由第一内插滤波器组提供的相位，并且更新相位偏移值以产生 作出决定。 插入在均衡级之间的第一内插滤波器组的装置被配置为产生到最后的均衡级的相位偏移信号，并且响应于最后的均衡级的相位偏移环被配置为调整由第一内插滤波器组提供的相位偏移 。

公开(公告)号：US09106462B1

公开(公告)日：2015-08-11

申请号：US14336986

申请日：2014-07-21

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Amaresh V. Malipatil ,  Mohammad S. Mobin

IPC: H04L25/04 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L2025/03694 ,  H04L2025/037

Abstract: Described embodiments include a process and apparatus that takes into account the operating voltage and temperature (VT) variations of a SERDES receiver implemented in an integrated circuit (IC) or system-on-chip (SoC). An analog equalizer (AEQ) adaptation loop and a decision feedback equalizer (DFE) adaptation loop are disabled after the loops have converged or stabilized the parameters of the AEQ and DFE. While the AFE and DFE adaptation loops are disabled, certain monitor coefficients related to signals corrected by the AFE and DFE are adapted and metrics derived therefrom are generated. The metrics are compared to threshold values to check if they have sufficiently changed over time to warrant re-enabling of the AFE and DFE adaptation loops.

Abstract translation: 所描述的实施例包括考虑在集成电路（IC）或片上系统（SoC）中实现的SERDES接收器的工作电压和温度（VT）变化的过程和装置。 在环路收敛或稳定AEQ和DFE的参数之后，禁用模拟均衡器（AEQ）适配环路和判决反馈均衡器（DFE）适配环路。 当AFE和DFE自适应环路被禁用时，与由AFE和DFE校正的信号有关的某些监视系数被调整，并且产生从其导出的度量。 将度量与阈值进行比较，以检查它们是否随时间发生充分变化，以保证AFE和DFE适配环路的重新启用。