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    Non-Linear Interference Cancellation For Wireless Transceivers
    11.
    发明申请
    Non-Linear Interference Cancellation For Wireless Transceivers 有权
    无线收发器的非线性干扰消除

    公开(公告)号：US20140313946A1

    公开(公告)日：2014-10-23

    申请号：US14230635

    申请日：2014-03-31

    申请人： LSI Corporation

    发明人： Kameran Azadet

    IPC分类号： H04L5/14 ,  H04L25/08

    CPC分类号： H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    摘要： Non-linear interference cancellation techniques are provided for wireless transceivers. Non-linear reduction of interference of a transmit signal on a received signal in a transceiver device, comprises applying the transmit signal to a first non-linear system; applying the received signal to a second non-linear system; and subtracting an output of the first non-linear system output from an output of second non-linear system output to produce an interference mitigated received signal. The first non-linear system and/or the second non-linear system can be to implemented using one or more of a Volterra series and a Generalized Memory Polynomial Model. System parameters of the first non-linear system and/or the second non-linear system are adapted to reduce a power of the interference mitigated received signal.

    摘要翻译： 为无线收发器提供非线性干扰消除技术。 发射信号对收发器设备中的接收信号的干扰的非线性减小包括将发射信号应用于第一非线性系统; 将接收的信号应用于第二非线性系统; 以及从第二非线性系统输出的输出中减去输出的第一非线性系统的输出以产生干扰减轻的接收信号。 第一非线性系统和/或第二非线性系统可以使用Volterra系列和广义存储器多项式模型中的一个或多个实现。 第一非线性系统和/或第二非线性系统的系统参数适于减小干扰减轻的接收信号的功率。

    Method and Apparatus for High Density Pulse Density Modulation
    12.
    发明申请
    Method and Apparatus for High Density Pulse Density Modulation 有权
    高密度脉冲密度调制方法与装置

    公开(公告)号：US20140119427A1

    公开(公告)日：2014-05-01

    申请号：US13663534

    申请日：2012-10-30

    申请人： LSI CORPORATION

    发明人： Donald R. Laturell ,  Said E. Abdelli ,  Peter Kiss ,  James F. MacDonald ,  Ross S. Wilson ,  Kameran Azadet

    IPC分类号： H04L27/04

    CPC分类号： H04L27/04 ,  H03F3/217 ,  H03F3/24 ,  H03F3/60 ,  H03G11/002 ,  H03M5/04

    摘要： A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.

    摘要翻译： 公开了一种用于高密度脉冲密度调制的方法和系统。 根据本公开，使用互补的一对非线性函数将调制功能分为两个频带限制流。 更具体地，一个比特流定义包含原始功能的峰值，而另一个比特流包含原始比特流的软限幅版本。 比特流被施加到一对开关放大器，并且可以再次组合比特流以重建原始功能。 根据本公开的方法限制了实现更高输出功率所需的输入功率量，降低了工作电压并提高了功率放大器的效率。

    MULTI-STAGE CREST FACTOR REDUCTION (CFR) FOR MULTI-CHANNEL MULTI-STANDARD RADIO
    14.
    发明申请
    MULTI-STAGE CREST FACTOR REDUCTION (CFR) FOR MULTI-CHANNEL MULTI-STANDARD RADIO 有权
    用于多通道多标准无线电的多阶段检测因子减少（CFR）

    公开(公告)号：US20130114761A1

    公开(公告)日：2013-05-09

    申请号：US13661351

    申请日：2012-10-26

    申请人： LSI Corporation

    发明人： Kameran Azadet ,  Albert Molina

    IPC分类号： H04B1/04

    CPC分类号： G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

    摘要： Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of the first and second individual crest factor reduction blocks to generate an aggregated output; and applying the aggregated output to a composite crest factor reduction block. The individual crest factor reduction blocks can be implemented using a sampling rate appropriate for the corresponding technology type. The composite crest factor reduction block operates at a higher sampling rate than the individual crest factor reduction blocks.

    摘要翻译： 为多通道多标准无线电（MSR）提供多级波峰因数降低（CFR）技术。 多级波峰因数降低方法包括将与第一技术类型的至少一个信道相关联的一个或多个数据样本应用于第一单独波峰因数减少块; 将与第二技术类型的至少一个信道相关联的一个或多个数据样本应用于第二单独波峰因子减小块; 聚合第一和第二单独波峰因子减小块的输出以生成聚合输出; 并将聚合输出应用于复合波峰因数减少块。 可以使用适合于相应技术类型的采样率来实现各个波峰因数减小块。 复合波峰因数降低块以比单个波峰因数减小块更高的采样速率运行。

    Switching power amplifier system for multi-path signal interleaving
    15.
    发明授权
    Switching power amplifier system for multi-path signal interleaving 有权
    用于多路信号交错的开关功率放大器系统

    公开(公告)号：US09106207B2

    公开(公告)日：2015-08-11

    申请号：US13709743

    申请日：2012-12-10

    申请人： LSI Corporation

    发明人： Peter Kiss ,  Said E. Abdelli ,  Kameran Azadet ,  Donald R. Laturell ,  James F. MacDonald ,  Ross S. Wilson

    IPC分类号： H03F3/68 ,  H03H11/00 ,  H03F3/217 ,  H03F3/24 ,  H03M3/00

    CPC分类号： H03H11/00 ,  H03F3/2175 ,  H03F3/24 ,  H03M3/50

    摘要： A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

    摘要翻译： 一种用于多径信号交织的开关功率放大器包括：信号分配器，被配置为将来自数字源的多位源信号分离成多个多位信号;一个或多个分数延迟滤波器，被配置为延迟一个或多个信号 所述多个信号经过选定的时间，多个比特流转换器，每个比特流转换器被配置为接收所述多比特信号中的一个，每个比特流转换器还被配置为基于所述多比特信号生成单比特信号 接收的多位信号，多个开关功率放大器，每个开关功率放大器被配置为从位流转换器之一接收单位信号;以及交织器，被配置为通过交织两个或多个输出 开关功率放大器，其中交织器的交错输出的采样频率大于所选择的多位源信号的采样频率。

    Non-Linear Modeling of a Physical System Using Look-Up Table with Polynomial Interpolation
    16.
    发明申请
    Non-Linear Modeling of a Physical System Using Look-Up Table with Polynomial Interpolation 有权
    使用具有多项式插值的查找表的物理系统的非线性建模

    公开(公告)号：US20140314181A1

    公开(公告)日：2014-10-23

    申请号：US14230622

    申请日：2014-03-31

    申请人： LSI Corporation

    发明人： Kameran Azadet

    IPC分类号： H04L1/00 ,  H04B1/62 ,  G06F17/50

    CPC分类号： H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    摘要： Methods and apparatus are provided for non-linear modeling of a physical system using look-up tables with polynomial interpolation. A non-linear function is evaluated for a complex input value by obtaining at least one look-up table with polynomial interpolation that represents the non-linear function, wherein entries in the look-up table comprise polynomial coefficients of at least degree two for different segments of the non-linear function; obtaining a point from the look-up table that is near a magnitude of the complex input value; and generating a complex output value by evaluating the polynomial coefficients at the point to perform a Taylor Series expansion from said point. The non-linear function characterizes, for example, a power amplifier or an inverse of a power amplifier and the look-up tables can be used, for example, to implement digital pre-distortion. The look-up table can be stored in a memory of a digital processor, and the polynomial interpolation can be performed as part of a user-defined non-linear instruction that takes a complex number as an input, x, and computes ƒ(x).

    摘要翻译： 提供了使用具有多项式插值的查找表对物理系统进行非线性建模的方法和装置。 通过获得表示非线性函数的多项式插值的至少一个查找表来对复数输入值评估非线性函数，其中查找表中的条目包括至少二等于不同的多项式系数 段的非线性函数; 从所述查找表获得接近复数输入值的大小的点; 以及通过评估从所述点执行泰勒级数展开的点处的多项式系数来产生复数输出值。 非线性功能表征例如功率放大器或功率放大器的反相，并且可以使用查找表来实现数字预失真。 查找表可以存储在数字处理器的存储器中，并且多项式插值可以作为将复数作为输入x的用户定义的非线性指令的一部分来执行，并且计算ƒ（x ）。

    Non-Linear Modeling of a Physical System Using Two-Dimensional Look-Up Table with Bilinear Interpolation
    17.
    发明申请
    Non-Linear Modeling of a Physical System Using Two-Dimensional Look-Up Table with Bilinear Interpolation 有权
    使用具有双线性插值的二维查找表的物理系统的非线性建模

    公开(公告)号：US20140314176A1

    公开(公告)日：2014-10-23

    申请号：US14230607

    申请日：2014-03-31

    申请人： LSI CORPORATION

    发明人： Kameran Azadet

    IPC分类号： H04L1/00 ,  H04B1/62 ,  G06F17/50

    CPC分类号： H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

    摘要： Methods and apparatus are provided for non-linear modeling of a physical system using two-dimensional look-up tables with bilinear interpolation. A non-linear function is evaluated for a complex input value by obtaining a two-dimensional (2D) look-up table with bilinear interpolation that represents the non-linear function; obtaining four points from the 2D look-up table that are in a vicinity of the complex input value; and generating a complex output value comprised of a bilinear combination of the four points. The non-linear function characterizes, for example, a power amplifier or an inverse of a power amplifier and the 2D look-up tables can be used, for example, to implement digital pre-distortion. The 2D look-up tables with bilinear interpolation can be used in a processor instruction as part of an instruction set of one or more of a scalar processor and a vector processor.

    摘要翻译： 提供了使用具有双线性插值的二维查找表对物理系统进行非线性建模的方法和装置。 通过获得表示非线性函数的双线性插值的二维（2D）查找表，对复数输入值评估非线性函数; 从2D查找表中获得四分之一的复数输入值附近; 以及生成由四个点的双线性组合组成的复合输出值。 非线性功能表征例如功率放大器或功率放大器的反相，并且可以使用2D查找表，例如来实现数字预失真。 具有双线性插值的2D查找表可以在处理器指令中用作标量处理器和向量处理器中的一个或多个的指令集的一部分。

    BiCMOS gate driver for class-S radio frequency power amplifier
    18.
    发明授权
    BiCMOS gate driver for class-S radio frequency power amplifier 有权
    用于S类射频功率放大器的BiCMOS栅极驱动器

    公开(公告)号：US08760225B1

    公开(公告)日：2014-06-24

    申请号：US13736442

    申请日：2013-01-08

    申请人： LSI Corporation

    发明人： Ross S. Wilson ,  Said E. Abdelli ,  Peter Kiss ,  Donald R. Laturell ,  Kameran Azadet ,  James F. MacDonald

    IPC分类号： H03F3/38

    CPC分类号： H03F3/2171 ,  H03F3/193 ,  H03F3/195 ,  H03F3/245 ,  H03F3/305 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/78 ,  H03F2203/45394 ,  H03F2203/45456 ,  H03F2203/45631 ,  H03F2203/45702

    摘要： The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems.

    摘要翻译： 本发明可以体现在用于驱动数字S类射频功率放大器（RF-PA）的栅电极的再同步推挽驱动电路中。 从比特流发生器（例如，Σ-Δ调制器，基于维特比的最佳位模式调制器Σ-Δ或其它合适的调制器）接收的二进制比特流被重新同步到低抖动主时钟， 上升，高挥发互补数字信号驱动S-S RF-PA的门。 驱动电路提供高压摆率，大摆幅，准数字栅极驱动电路，以足够的上升时间驱动RF-PA的显着栅极电容。 采用双极晶体管电流开关和级联CMOS器件的组合来实现必要的性能。 例如，驱动电路非常适用于无线通信系统中使用的S类RF-PA。