BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES
    16.
    发明申请
    BIT CELL WITH DOUBLE PATTERNED METAL LAYER STRUCTURES 有权
    具有双重图案的金属层结构的位单元

    公开(公告)号:US20140077380A1

    公开(公告)日:2014-03-20

    申请号:US13617853

    申请日:2012-09-14

    IPC分类号: H01L21/28 H01L29/41

    摘要: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

    摘要翻译: 公开了一种提供具有双图案化金属层结构的SRAM位单元的方法。 实施例包括:经由第一图案化工艺提供字线结构,接地线结构,电力线结构或其组合; 以及经由第二图案化处理提供靠近所述字线结构,所述接地线结构,所述电力线结构或其组合的位线结构。 实施例包括:提供作为字线结构的第一着陆焊盘和作为接地线结构的第二着陆焊盘; 以及提供所述第一着陆垫具有第一末端边缘和第一侧边缘,并且所述第二着陆垫具有第二末端边缘和第二侧边缘,其中所述第一侧边缘面向所述第二侧边缘。

    Software and method for via spacing in a semiconductor device
    18.
    发明授权
    Software and method for via spacing in a semiconductor device 有权
    用于半导体器件中通孔间隔的软件和方法

    公开(公告)号:US08859416B2

    公开(公告)日:2014-10-14

    申请号:US13454928

    申请日:2012-04-24

    IPC分类号: H01L21/768

    摘要: A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.

    摘要翻译: 提供了一种用于执行确定半导体器件中多个电力轨道通孔的位置的方法的计算机可读软件产品。 半导体器件包括有源区和电源轨。 沿着电源轨分配第一通孔和第二通孔的位置。 第一通孔的位置与第二通孔的位置之间的间隔是允许的最小间隔。 确定第二通孔的位置与可能与第二通孔电干扰的有源区域中结构的位置之间的间隔。 响应于第二通孔的位置与有源区域中的一个结构的位置之间的间隔小于预定距离而改变第二通孔的位置。

    SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE
    20.
    发明申请
    SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE 有权
    用于通过半导体器件间隔的软件和方法

    公开(公告)号:US20130280905A1

    公开(公告)日:2013-10-24

    申请号:US13454928

    申请日:2012-04-24

    IPC分类号: H01L21/768 G06F17/50

    摘要: A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance.

    摘要翻译: 提供了一种用于执行确定半导体器件中多个电力轨道通孔的位置的方法的计算机可读软件产品。 半导体器件包括有源区和电源轨。 沿着电源轨分配第一通孔和第二通孔的位置。 第一通孔的位置与第二通孔的位置之间的间隔是允许的最小间隔。 确定第二通孔的位置与可能与第二通孔电干扰的有源区域中结构的位置之间的间隔。 响应于第二通孔的位置与有源区域中的一个结构的位置之间的间隔小于预定距离而改变第二通孔的位置。