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11.发明授权Method and apparatus for performing add and rotate as a single instruction within a processor 失效用于在处理器内作为单个指令执行加法和旋转的方法和装置
公开(公告)号：US5881274A
公开(公告)日：1999-03-09
申请号：US900261
申请日：1997-07-25
申请人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
发明人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
CPC分类号： G06F9/3001 , G06F9/30032
摘要： An apparatus for performing ADD and ROTATE as a single instruction within a processor is disclosed. In accordance with a preferred embodiment of the present invention, the apparatus comprises an adder and a rotator. The adder is utilized for adding a first number to a second number in a multiple stages to yield a carry-out and a sum output. During each of these stages, the adder produces a group generate value and a group propagate value. The rotator is utilized for rotating the group propagate value and the group generate value at each of the stages before the yielding of the carry-out and the sum output. As such, both ADD and ROTATE instructions can be completed within a single processor cycle.
摘要翻译： 公开了一种用于在处理器内执行ADD和ROTATE作为单个指令的装置。 根据本发明的优选实施例，该装置包括加法器和旋转器。 加法器用于将多个第一数字加到多个第二数目中以产生一个进位输出和一个和输出。 在每个阶段中，加法器产生组生成值和组传播值。 旋转器用于旋转组传播值，并且在进位输出和总和输出的屈服之前的组中的每个级产生组生成值。 因此，ADD和ROTATE指令都可以在单个处理器周期内完成。
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公开(公告)号：US08127116B2
公开(公告)日：2012-02-28
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译： 具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。 第二阵列耦合到第一阵列并且包括多个第二单元。 第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。 第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。 第二个读取端口耦合到第一个数组并从第一个数组读取。 第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。
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13.发明申请Method and System for Restoring Register Mapper States for an Out-Of-Order Microprocessor 失效用于为无序微处理器恢复寄存器映射器状态的方法和系统公开(公告)号：US20080195850A1
公开(公告)日：2008-08-14
申请号：US11674754
申请日：2007-02-14
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译： 一种恢复无序微处理器的寄存器映射器状态的方法。 处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。 指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态 位图中的数据结构。
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公开(公告)号：US07079409B2
公开(公告)日：2006-07-18
申请号：US10899358
申请日：2004-07-26
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： This invention reduces power consumed during CAM search operations in a CAM/RAM structure utilizing a segmented match line structure. This device is useful when it is known that a portion or portions of the compare data inputs vary infrequently. The apparatus sometimes may be referred to as local match line hold latch, and is a device that stores the value of a local match line comparison result the first time that a search operation occurs, and will stay at that value until the value of the compare data in of the local match line changes.
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公开(公告)号：US08809995B2
公开(公告)日：2014-08-19
申请号：US13408300
申请日：2012-02-29
申请人： Xiaomin Duan , Xiaoxiong Gu , Yong Liu , Joel A. Silberman
发明人： Xiaomin Duan , Xiaoxiong Gu , Yong Liu , Joel A. Silberman
IPC分类号： H01L23/528
CPC分类号： H01L23/481 , H01L23/535 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： Circuits for shielding devices from electromagnetic coupling with through-silicon vias are shown that include a substrate having a through via, which provides access to a device layer on a first surface of the circuit to a device layer on a second surface of the circuit; a conductive layer on the first side of the substrate; a contact point on one of the device layers; and a grounded buried interface tie on the conductive layer, adjacent to the contact point, to isolate the contact point from coupling noise.
摘要翻译： 示出了用于屏蔽器件与通过硅通孔的电磁耦合的电路，其包括具有通孔的衬底，其提供对电路的第一表面上的器件层的访问到电路的第二表面上的器件层; 在所述基板的第一侧上的导电层; 一个设备层上的接触点; 以及在接触点附近的导电层上的接地埋入界面，以将接触点与耦合噪声隔离。
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16.发明申请公开(公告)号：US20130221484A1
公开(公告)日：2013-08-29
申请号：US13408300
申请日：2012-02-29
申请人： Xiaomin Duan , Xiaoxiong Gu , Yong Liu , Joel A. Silberman
发明人： Xiaomin Duan , Xiaoxiong Gu , Yong Liu , Joel A. Silberman
IPC分类号： H01L23/48 , H01L21/768 , H01L29/92
CPC分类号： H01L23/481 , H01L23/535 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： Circuits for shielding devices from electromagnetic coupling with through-silicon vias are shown that include a substrate having a through via, which provides access to a device layer on a first surface of the circuit to a device layer on a second surface of the circuit; a conductive layer on the first side of the substrate; a contact point on one of the device layers; and a grounded buried interface tie on the conductive layer, adjacent to the contact point, to isolate the contact point from coupling noise.
摘要翻译： 示出了用于屏蔽器件与通过硅通孔的电磁耦合的电路，其包括具有通孔的衬底，其提供对电路的第一表面上的器件层的访问到电路的第二表面上的器件层; 在所述基板的第一侧上的导电层; 一个设备层上的接触点; 以及在接触点附近的导电层上的接地埋入界面，以将接触点与耦合噪声隔离。
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公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译： 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。
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18.发明授权Method and system for restoring register mapper states for an out-of-order microprocessor 失效用于恢复无序微处理器的寄存器映射器状态的方法和系统公开(公告)号：US07689812B2
公开(公告)日：2010-03-30
申请号：US11674754
申请日：2007-02-14
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译： 一种恢复无序微处理器的寄存器映射器状态的方法。 处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。 当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。 指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态 位图中的数据结构。
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19.发明申请Using a Register File as Either a Rename Buffer or an Architected Register File 审中-公开使用注册文件作为重命名缓冲区或建筑注册表文件公开(公告)号：US20080244242A1
公开(公告)日：2008-10-02
申请号：US11695303
申请日：2007-04-02
IPC分类号： G06F7/38
CPC分类号： G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3857 , G06F9/3885
摘要： A computer implemented method, apparatus, and computer usable program code are provided for implementing a set of architected register files as a set of temporary rename buffers. An instruction dispatch unit receives an instruction that includes instruction data. The instruction dispatch unit determines a thread mode under which a processor is operating. Responsive to determining the thread mode, the instruction dispatch unit determines an ability to use the set of architected register files as the set of temporary rename buffers. Responsive to the ability to use the set of architected register files as the set of temporary rename buffers, the instruction dispatch unit analyzes the instruction to determine an address of an architected register file in the set of architected register files where the instruction data is to be stored. The architected register file operating as a temporary rename buffer stores the instruction data as finished data.
摘要翻译： 提供了一种计算机实现的方法，装置和计算机可用程序代码，用于将一组架构化的寄存器文件实现为一组临时重命名缓冲器。 指令分配单元接收包括指令数据的指令。 指令调度单元确定处理器在其下操作的线程模式。 响应于确定线程模式，指令分派单元确定使用一组架构化寄存器文件作为临时重命名缓冲器集合的能力。 响应于使用该组建筑寄存器文件作为一组临时重命名缓冲器的能力，指令分派单元分析该指令以确定在该指令数据将被设置的一组架构化寄存器文件集中的架构化寄存器文件的地址 存储。 作为临时重命名缓冲区运行的架构化寄存器文件将指令数据存储为完成的数据。
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公开(公告)号：US07170328B2
公开(公告)日：2007-01-30
申请号：US10982112
申请日：2004-11-05
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译： 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。
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