公开(公告)号：US06774000B2

公开(公告)日：2004-08-10

申请号：US10300239

申请日：2002-11-20

申请人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21336

CPC分类号： H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

公开(公告)号：US07485965B2

公开(公告)日：2009-02-03

申请号：US11753617

申请日：2007-05-25

申请人： Louis D. Lanzerotti ,  Max G. Levy ,  Yun Shi ,  Steven H. Voldman

发明人： Louis D. Lanzerotti ,  Max G. Levy ,  Yun Shi ,  Steven H. Voldman

IPC分类号： H01L27/01

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate. Also disclosed is a method for providing a wafer varied resistivity using the through vias and buried dielectric.

摘要翻译： 公开了一种超高电阻率晶圆的通孔和相关方法。 形成通孔的方法包括：提供包括第一硅层，埋入介质层和基底的半导体晶片; 在第一硅上形成器件; 以及从所述衬底的与所述掩埋介电层相对的一侧并通过所述衬底形成通孔。 还公开了一种使用通孔和埋入电介质提供晶片变化的电阻率的方法。

公开(公告)号：US06858903B2

公开(公告)日：2005-02-22

申请号：US10881449

申请日：2004-06-30

申请人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

发明人： Wesley C. Natzle ,  Marc W. Cantell ,  Louis D. Lanzerotti ,  Effendi Leobandung ,  Brian L. Tessier ,  Ryan W. Wuthrich

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L27/76

CPC分类号： H01L21/31116 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/66628

摘要： A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

摘要翻译： 一种用于制造FET器件的工艺。 半导体衬底被栅极电介质层覆盖，并且在栅极电介质上形成导电栅电极。 可以加入氧化硅的毯层。 可以在栅电极周围的氧化硅层上形成可选的氮化硅环。 执行两个预清洗步骤。 然后沉积化学氧化物去除气体，用吸附的反应物膜覆盖该装置。 由于吸附的反应物膜与栅极电介质层反应，在栅电极的底部形成氧化硅的圆角，所以除去栅极电介质（除了栅电极之外）。 一个或两个原位掺杂的硅层沉积在源极/漏极区上，以在衬底上方突出超过栅极电介质的表面形成单个或层叠的外延凸起的源/漏区。

公开(公告)号：US06441462B1

公开(公告)日：2002-08-27

申请号：US09682016

申请日：2001-07-10

申请人： Louis D. Lanzerotti ,  Steven H. Voldman

发明人： Louis D. Lanzerotti ,  Steven H. Voldman

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

摘要： A semiconductor bipolar transistor structure having improved electrostatic discharge (ESD) robustness is provided as well as a method of fabricating the same. Specifically, the inventive semiconductor structure a semiconductor structure comprises a bipolar transistor comprising a lightly doped intrinsic base; a heavily doped extrinsic base adjacent to said intrinsic base, a heavily doped/lightly doped base doping transition edge therebetween, said heavily doped/lightly doped base doping transition edge defined by an edge of a window; and a silicide region extending on said extrinsic base, wherein said silicide region is completely outside said window.

摘要翻译： 提供了具有改善的静电放电（ESD）稳定性的半导体双极晶体管结构及其制造方法。 具体地，本发明的半导体结构是半导体结构，包括：包含轻掺杂的本征基极的双极晶体管; 与所述本征基极相邻的重掺杂的外部基极，其间的重掺杂/轻掺杂的基极掺杂跃迁边缘，由窗口的边缘限定的所述重掺杂/轻掺杂的基极掺杂过渡边缘; 以及在所述外部基极上延伸的硅化物区域，其中所述硅化物区域完全在所述窗口的外部。

公开(公告)号：US20080290524A1

公开(公告)日：2008-11-27

申请号：US11753617

申请日：2007-05-25

申请人： Louis D. Lanzerotti ,  Max G. Levy ,  Yun Shi ,  Steven H. Voldman

发明人： Louis D. Lanzerotti ,  Max G. Levy ,  Yun Shi ,  Steven H. Voldman

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate.

摘要翻译： 公开了一种超高电阻率晶圆的通孔和相关方法。 形成通孔的方法包括：提供包括第一硅层，埋入介质层和基底的半导体晶片; 在第一硅上形成器件; 以及从所述衬底的与所述掩埋介电层相对的一侧并通过所述衬底形成通孔。

公开(公告)号：US07202136B2

公开(公告)日：2007-04-10

申请号：US11121454

申请日：2005-05-04

申请人： Louis D. Lanzerotti ,  Brian P. Ronan ,  Steven H. Voldman

发明人： Louis D. Lanzerotti ,  Brian P. Ronan ,  Steven H. Voldman

IPC分类号： H01L21/331 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01H85/47 ,  H01L29/7378

摘要： A silicon germanium heterojunction bipolar transistor device and method comprises a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5–25% germanium and 0–3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

摘要翻译： 硅锗异质结双极晶体管器件和方法包括半导体区域和半导体区域中的扩散区域，其中扩散区域是硼掺杂的，其中半导体区域包括其中的碳掺杂剂以最小化硼扩散，并且其中组合 的掺杂剂的量，硼的量和半导体区域的尺寸使得扩散区域具有小于约4Kohms / cm 2的薄层电阻。 此外，扩散区域以1×10 20 / cm 3至1×10 21 / cm 3的浓度硼掺杂， SUP>。 另外，半导体区域包括5-25％的锗和0-3％的碳。 通过向半导体区域添加碳，该器件实现了静电放电鲁棒性，这进一步导致器件的功率故障分布更严格，并且增加了临界厚度并降低了半导体区域的热应变。

公开(公告)号：US07173274B2

公开(公告)日：2007-02-06

申请号：US10953378

申请日：2004-09-29

申请人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0339

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US07138669B2

公开(公告)日：2006-11-21

申请号：US10660048

申请日：2003-09-11

申请人： Louis D. Lanzerotti ,  Brian P. Ronan ,  Steven H. Voldman

发明人： Louis D. Lanzerotti ,  Brian P. Ronan ,  Steven H. Voldman

IPC分类号： H01L29/739 ,  H01L27/02

CPC分类号： H01L29/66242 ,  H01H85/47 ,  H01L29/7378

摘要： A silicon germanium heterojunction bipolar transistor device and method comprises a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5–25% germanium and 0–3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

摘要翻译： 硅锗异质结双极晶体管器件和方法包括半导体区域和半导体区域中的扩散区域，其中扩散区域是硼掺杂的，其中半导体区域包括其中的碳掺杂剂以最小化硼扩散，并且其中组合 的掺杂剂的量，硼的量和半导体区域的尺寸使得扩散区域具有小于约4Kohms / cm 2的薄层电阻。 此外，扩散区域以1×10 20 / cm 3至1×10 21 / cm 3的浓度硼掺杂， SUP>。 另外，半导体区域包括5-25％的锗和0-3％的碳。 通过向半导体区域添加碳，该器件实现了静电放电鲁棒性，这进一步导致器件的功率故障分布更严格，并且增加了临界厚度并降低了半导体区域的热应变。

公开(公告)号：US06670654B2

公开(公告)日：2003-12-30

申请号：US09683498

申请日：2002-01-09

申请人： Louis D. Lanzerotti ,  Brian P. Ronan ,  Steven H. Voldman

发明人： Louis D. Lanzerotti ,  Brian P. Ronan ,  Steven H. Voldman

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01H85/47 ,  H01L29/7378

摘要： A silicon germanium heterojunction bipolar transistor device having a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5-25% germanium and 0-3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

摘要翻译： 具有半导体区域的硅锗异质结双极晶体管器件和半导体区域中的扩散区域，其中所述扩散区域是硼掺杂的，其中所述半导体区域包括其中的碳掺杂剂以使硼扩散最小化，并且其中， 掺杂剂的量，硼的量和半导体区域的尺寸使得扩散区域的薄层电阻小于约4Kohms / cm 2。 此外，扩散区域以1×10 20 / cm 3至1×10 21 / cm 3的浓度进行硼掺杂。 另外，半导体区域包括5-25％的锗和0-3％的碳。 通过向半导体区域添加碳，该器件实现了静电放电鲁棒性，这进一步导致器件的功率故障分布更严格，并且增加了临界厚度并降低了半导体区域的热应变。

公开(公告)号：US07956412B2

公开(公告)日：2011-06-07

申请号：US11950001

申请日：2007-12-04

申请人： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Louis D. Lanzerotti ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

发明人： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Louis D. Lanzerotti ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

IPC分类号： H01L29/417

CPC分类号： H01L29/7825 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7816

摘要： A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation.

摘要翻译： 介电材料层形成在半导体衬底的沟槽的底表面和侧壁上。 氧化硅层形成漂移区电介质，在其上形成场板。 可以在形成漂移区电介质之前形成浅沟槽隔离，或者可以利用与形成漂移区电介质相同的处理步骤来形成。 在暴露的半导体表面上形成栅极电介质层，并且在栅极介电层和漂移区电介质上形成栅极导体层。 场板可以电连接到栅电极，可以是具有外部偏置的独立电极，或者可以是浮置电极。 场板偏置漂移区域以增强性能并且在操作期间延长横向扩散场效应晶体管的允许工作电压。