摘要:
A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.
摘要:
A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.
摘要:
An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.
摘要:
The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.
摘要:
The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced base resistence. The preferred design forms the extrinsic base by diffusing dopants from a dopant source layer and into the extrinsic base region. This diffusion of dopants forms at least a portion of the extrinsic base. In particular, the portion adjacent to the intrinsic base region is formed by diffusion. This solution avoids the problems caused by traditional solutions that implanted the extrinsic base. Specifically, by forming at least a portion of the extrinsic base by diffusion, the problem of damage to base region is minimized. This reduced damage enhances dopant diffusion into the intrinsic base. Additionally, the formed extrinsic base can have improved resistence, resulting in an improved maximum frequency for the bipolar device. Additionally, the extrinsic base can be formed with a self-aligned manufacturing process that reduces fabrication complexity.
摘要:
A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.
摘要:
A method and structure for a transistor that includes an insulator and a silicon structure on the insulator. The silicon structure includes a central portion and Fins extending from ends of the central portion. A first gate is positioned on a first side of the central portion of the silicon structure. A strain-producing layer could be between the first gate and the first side of the central portion of the silicon structure and a second gate is on a second side of the central portion of the silicon structure.
摘要:
A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
摘要:
Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
摘要:
A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate. Also disclosed is a method for providing a wafer varied resistivity using the through vias and buried dielectric.