公开(公告)号：US20080175408A1

公开(公告)日：2008-07-24

申请号：US11757110

申请日：2007-06-01

申请人： Shridhar Mukund ,  Vivek Nigam

发明人： Shridhar Mukund ,  Vivek Nigam

IPC分类号： G10L21/02 ,  G10L21/00

CPC分类号： G10L21/0208

摘要： An audio signal enhancement device is provided. The device includes a first and a second microphone, placed as close together as possible, the first and second microphone having receiving surfaces facing in opposing directions. The first and second microphones receive a desired target audio signal originating in the proximity of the microphones and undesired noise signals not originating in the proximity of the microphones. The acoustic pressure gradient from the desired target signal between the first and the second microphones is greater than that from the noise signals. A signal processing logic is provided. The signal processing logic is configured to firstly generate a proximity-indicator signal and a pre-target-estimate signal through a combination of output from the first microphone and output of the second microphone. The signal processing logic is further configured to generate a noise-estimate signal by combining the output from the first microphone with the proximity-indicator and the pre-target-estimate. The signal processing logic is further configured to generate a target-estimate signal by combining the output from the first microphone with the proximity-indicator and the noise-estimate. The signal processing logic is further configured to provide a target signal substantially free from noise by combining the target-estimate, noise-estimate and the proximity-indicator.

摘要翻译： 提供一种音频信号增强装置。 该装置包括第一麦克风和第二麦克风，其尽可能靠近放置，第一和第二麦克风具有面向相反方向的接收表面。 第一和第二麦克风接收始发于麦克风附近的期望的目标音频信号和不是源于麦克风附近的不期望的噪声信号。 来自第一麦克风和第二麦克风之间的期望目标信号的声压梯度大于来自噪声信号的声压级梯度。 提供信号处理逻辑。 信号处理逻辑被配置为首先通过来自第一麦克风的输出和第二麦克风的输出的组合产生接近指示符信号和预定目标估计信号。 所述信号处理逻辑还被配置为通过将来自所述第一麦克风的输出与所述接近指示符和所述预先目标估计相结合来产生噪声估计信号。 信号处理逻辑还被配置为通过组合来自第一麦克风的输出与接近指示符和噪声估计来产生目标估计信号。 信号处理逻辑还被配置为通过组合目标估计，噪声估计和接近度指标来提供基本上没有噪声的目标信号。

公开(公告)号：US20060294483A1

公开(公告)日：2006-12-28

申请号：US11426880

申请日：2006-06-27

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。

公开(公告)号：US06901496B1

公开(公告)日：2005-05-31

申请号：US10264580

申请日：2002-10-04

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： H04L29/06 ,  G06F12/00

CPC分类号： H04L69/12

摘要： A network interface card is provided. The network interface card includes a plurality of pipelined processors. Each of the pipelined processors includes an input socket having at least three single ported memory regions configured to store variable-size data packets. The at least three single ported memory regions enable a downstream processor reading the variable-size data packets from the single ported memory regions to maintain a data throughput to support an incoming line rate of a data stream. The line rate data throughput is maintained after a maximum size data packet has been read by the downstream processor. Methods of method for optimizing throughput between a producing processor and a consuming processor and a processor are also provided.

摘要翻译： 提供网络接口卡。 网络接口卡包括多个流水线处理器。 每个流水线处理器包括具有至少三个单端口存储区域的输入套接字，其被配置为存储可变大小的数据分组。 所述至少三个单端口存储器区域使得下游处理器能够从单个端口存储器区域读取可变大小的数据分组，以维持数据吞吐量以支持数据流的输入线路速率。 在下游处理器读取最大尺寸数据包之后，维持线路速率数据吞吐量。 还提供了用于优化生产处理器和消费处理器和处理器之间的吞吐量的方法的方法。

公开(公告)号：US06804812B2

公开(公告)日：2004-10-12

申请号：US10458892

申请日：2003-06-10

申请人： Robert Osann, Jr. ,  Patrick Hallinan ,  Jung Lee ,  Shridhar Mukund

发明人： Robert Osann, Jr. ,  Patrick Hallinan ,  Jung Lee ,  Shridhar Mukund

IPC分类号： G06F1750

CPC分类号： H03K19/17708

摘要： A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.

摘要翻译： 根据本发明的可编程逻辑阵列（PLA）实现可编程连接的最大量的减少，同时仍然实现逻辑功能并保持将来重新编程的灵活性。 此外，可以构建根据本发明的PLA，使得无论编程什么功能，维护设备的性能特性。 此外，根据本发明的PLA不需要规则的阵列结构。

公开(公告)号：US08332197B2

公开(公告)日：2012-12-11

申请号：US10712711

申请日：2003-11-12

申请人： Shridhar Mukund ,  Jinesh Parikh

发明人： Shridhar Mukund ,  Jinesh Parikh

IPC分类号： G06F17/50 ,  G06F11/00 ,  G01R31/28

CPC分类号： G06F17/5022

摘要： A method for simulating a chip is provided. The method initiates with defining a library of components for a processor. Then, the interconnections for a set of pipelined processors including the processor are defined. Next, a processor circuit is generated by combining the library of components and the interconnections for the set of pipelined processors. Then, a code representation of a model of the set of pipelined processors is generated. Next, the signals generated by the code representation are compared to the signals generated by the processor circuit. If the comparison of the signals is unacceptable, then the method includes identifying a cause of the unacceptable comparison of the signals at a block level of the processor circuit. A method for generating a netlist for a pipeline of processors, a method for debugging the processor circuit and computer code for simulating a chip circuit are also provided.

摘要翻译： 提供了一种用于模拟芯片的方法。 该方法通过定义处理器的组件库来启动。 然后，定义一组包括处理器的流水线处理器的互连。 接下来，通过组合用于一组流水线处理器的组件库和互连来生成处理器电路。 然后，生成流水线处理器集合的模型的代码表示。 接下来，将由码表示产生的信号与由处理器电路产生的信号进行比较。 如果信号的比较是不可接受的，则该方法包括识别在处理器电路的块级别处的信号的不可接受的比较的原因。 还提供了一种用于生成处理器流水线的网表的方法，用于调试处理器电路的方法和用于模拟芯片电路的计算机代码。

公开(公告)号：US07877581B2

公开(公告)日：2011-01-25

申请号：US10726470

申请日：2003-12-02

申请人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

发明人： Shridhar Mukund ,  Mahesh Gopalan ,  Neeraj Kashalkar

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30025 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30032

摘要： A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.

摘要翻译： 提供了网络应用处理器。 处理器包括被配置为接收数据分组的输入套接字。 处理器包括用于保存指令的存储器和被配置为访问与处理级相关联的数据结构的电路。 被配置为访问数据结构的电路使得能够从存储器单元访问单个操作数。 提供了算术逻辑单元（ALU）。 包括用于对准由ALU处理的操作数的电路。 用于对准操作数的电路使操作数与最低有效位对齐，其中对准操作数的电路向操作数提供扩展以允许ALU处理不同大小的操作数。

公开(公告)号：US07571258B2

公开(公告)日：2009-08-04

申请号：US10718270

申请日：2003-11-19

申请人： Shridhar Mukund ,  Anjan Mitra ,  Mahesh Gopalan

发明人： Shridhar Mukund ,  Anjan Mitra ,  Mahesh Gopalan

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04J3/16 ,  H04J3/22 ,  G06F15/16

CPC分类号： H04L49/3063 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161

摘要： A method for efficiently processing layers of a data packet is provided. The method initiates with defining a pipeline of processors communicating with a distributed network and CPU of a host system. Then, a data packet from the distributed network is received into a first stage of the pipeline. Next, the data packet is processed to remove a header associated with the first stage. Then, the processed data packet is transmitted to a second stage. The operations of processing and transmitting the processed data packet are repeated for successive stages until a header associated with a final stage has been removed. Then, the data packet is transmitted to the CPU of the host system. It should be appreciated that the header is not necessarily transformed at each stage. For example, suitable processing that does not strip the header may be applied at each stage.

摘要翻译： 提供了一种用于有效处理数据分组的层的方法。 该方法通过定义与主机系统的分布式网络和CPU通信的处理器流水线来启动。 然后，来自分布式网络的数据分组被接收到流水线的第一级。 接下来，处理数据分组以移除与第一阶段相关联的报头。 然后，处理的数据分组被发送到第二阶段。 处理和发送处理的数据分组的操作重复连续阶段，直到与最后一级相关联的报头已经被去除。 然后，将数据包发送到主机系统的CPU。 应当理解，头部不一定在每个阶段变换。 例如，可以在每个阶段应用不剥离报头的适当处理。

公开(公告)号：US06223313B1

公开(公告)日：2001-04-24

申请号：US08985790

申请日：1997-12-05

申请人： Dana How ,  Adi Srinivasan ,  Robert Osann ,  Shridhar Mukund

发明人： Dana How ,  Adi Srinivasan ,  Robert Osann ,  Shridhar Mukund

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： A system for testing an integrated circuit, and particularly a gate array, is disclosed which includes, prior to coupling the array to form a user-designed circuit, predesigned logic that enables testing of the user-designed circuit. The predesigned logic allows logic blocks in the array to operate in “freeze” mode or to operate in normal mode, where normal mode is defined by the user-designed circuit. Much of the same circuitry in the logic blocks is, in fact, used in both modes of operation, thus minimizing circuitry added due to test. When the logic blocks are selected to be frozen, the logic blocks behave as a series of daisy-chained master-slave flip-flops. Stimulus data is shifted into the array and captured data is shifted out of the array through the daisy-chained flip-flops. Nonetheless, when data is shifted into and out of the daisy-chained flip-flops, the master latch and the slave latch of each flip-flop can be set to receive independent values and the data captured by each of the master and slave latches can be independently shifted out and analyzed. Although when frozen, the logic blocks behave as daisy-chained flip-flops, use of the logic blocks for testing purposes does not depend upon placement of sequential elements in the user-designed circuit in the logic blocks. In other words, in normal mode, a logic block can implement combinational, sequential, or other functions and still later be used to drive out stimulus values or capture results. Moreover, each logic block is further equipped for addressable mode control, allowing selected logic blocks to be exercised in isolation once stimulus data is shifted in, simplifying test generation and improving fault coverage. Using a logic block in accordance with the invention results in a high level of fault coverage, while placing few limitations on the user's circuit design.

摘要翻译： 公开了用于测试集成电路，特别是门阵列的系统，其包括在耦合阵列以形成用户设计的电路之前，预先设计的逻辑，其能够测试用户设计的电路。 预先设计的逻辑允许阵列中的逻辑块以“冻结”模式运行或在正常模式下运行，其中正常模式由用户设计的电路定义。 事实上，逻辑块中的大部分相同的电路用于两种工作模式，从而最小化由于测试而添加的电路。 当逻辑块被选择为冻结时，逻辑块表现为一系列菊花链主主机触发器。 激励数据移入阵列，捕获的数据通过菊花链式触发器从阵列中移出。 然而，当数据被移入和移出菊花链触发器时，每个触发器的主锁存器和从锁存器可被设置为接收独立的值，并且由每个主锁存器和从锁存器捕获的数据可以 独立移出并分析。 尽管在冻结时，逻辑块表现为菊花链式触发器，但用于测试目的的逻辑块的使用并不取决于逻辑块中用户设计的电路中顺序元件的位置。 换句话说，在正常模式下，逻辑块可以实现组合，顺序或其他功能，并且稍后可用于驱出刺激值或捕获结果。 此外，每个逻辑块进一步配置为可寻址模式控制，允许一旦激励数据被移位，孤立地选择逻辑块，简化测试生成并提高故障覆盖。 使用根据本发明的逻辑块导致高水平的故障覆盖，同时对用户的电路设计几乎没有限制。

公开(公告)号：US07783035B2

公开(公告)日：2010-08-24

申请号：US11612438

申请日：2006-12-18

申请人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

发明人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

IPC分类号： H04L9/00 ,  G06F15/16

CPC分类号： F04D29/703 ,  F04D29/388

摘要： A network node is disclosed. The network node includes a host processor. The network node also includes an integrated circuit. The integrated circuit includes a hardware portion configured to perform a first set of TCP acceleration tasks that require a first speed level. The integrated circuit also includes a network protocol processor configured to perform a second set of TCP acceleration tasks that require a second speed level, which is lower than the first speed level. The integrated circuit further includes an embedded processor configured to perform a third set of TCP acceleration tasks that require a third speed level, which is lower than the second speed level. The network node further includes a plurality of data paths configured to couple the integrated circuit to the host processor, the plurality of data paths being implemented based on different protocols.

摘要翻译： 公开了一种网络节点。 网络节点包括主机处理器。 网络节点还包括集成电路。 集成电路包括被配置为执行需要第一速度级别的第一组TCP加速任务的硬件部分。 集成电路还包括被配置为执行第二组TCP加速任务的网络协议处理器，其需要低于第一速度级别的第二速度级别。 集成电路还包括被配置为执行需要低于第二速度级别的第三速度级别的第三组TCP加速任务的嵌入式处理器。 网络节点还包括被配置为将集成电路耦合到主处理器的多个数据路径，所述多个数据路径是基于不同协议来实现的。

公开(公告)号：US20100008155A1

公开(公告)日：2010-01-14

申请号：US12561460

申请日：2009-09-17

申请人： Shridhar Mukund ,  Anjan Mitra

发明人： Shridhar Mukund ,  Anjan Mitra

IPC分类号： G11C7/10 ,  G06F17/50 ,  H03K19/003 ,  H03K19/173

CPC分类号： G06F17/505 ,  G06F15/7821 ,  G06F15/7867 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/5068 ,  Y02D10/12 ,  Y02D10/13

摘要： A semiconductor memory device is provided. The semiconductor memory device includes a plurality of memory cells arranged in multiple column groups, each column group having, a plurality of columns and a plurality of external bit-lines for independent multi-way configurable access. The column group having a first, second, and third level of hierarchy in the external bit-lines. The first level of the hierarchy provides connectivity to the plurality of memory cells. The second level of the hierarchy provides a first splicer for multiplexing data to and from each of the columns in the column group to an intermediate bit-line. The third level of the hierarchy includes a second splicer for multiplexing data to and from multiple external access paths to the intermediate bit-line. A structurally reconfigurable circuit device and methods for designing a circuit are also provided.

摘要翻译： 提供半导体存储器件。 半导体存储器件包括布置在多个列组中的多个存储器单元，每个列组具有用于独立多路可配置存取的多个列和多个外部位线。 列组在外部位线中具有第一，第二和第三层级。 层级的第一级提供与多个存储器单元的连接。 层级的第二级提供了用于将数据从列组中的每个列复用到中间位线的第一拼接器。 该层级的第三级包括用于将数据复用到从多个外部访问路径到中间位线的数据的第二拼接器。 还提供了一种结构可重构电路装置和用于设计电路的方法。