公开(公告)号：US11823751B2

公开(公告)日：2023-11-21

申请号：US17679170

申请日：2022-02-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A memory device and an operation method thereof are provided. The operation method includes: when a read operation or a write-verify operation is completed, during a word line voltage lowering phase, synchronously applying a plurality of different gradually lowering signal line reference voltages to a plurality of ground select lines and a plurality of string select lines, wherein values of the different gradually lowering signal line reference voltages are corresponding to a plurality of signal line positions of the ground select lines and the string select lines.

公开(公告)号：US20190067246A1

公开(公告)日：2019-02-28

申请号：US15683850

申请日：2017-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Chu-Yung Liu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L25/065 ,  H01L21/02 ,  H01L21/768

Abstract: A semiconductor structure includes a substrate, a stack of alternate conductive layers and insulating layers, a hole, and an active structure. The stack is disposed on the substrate. The conductive layers include an ith conductive layer and a jth conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness ti, the jth conductive layer has a thickness tj, and tj is larger than ti. The hole penetrates through the stack. The hole has a diameter Di and a diameter Dj corresponding to the ith conductive layer and the jth conductive layer, respectively, and Dj is larger than Di. The active structure is disposed in the hole. The active structure includes a channel layer. The channel layer is disposed along a sidewall of the hole and isolated from the conductive layers of the stack.

公开(公告)号：US20180158950A1

公开(公告)日：2018-06-07

申请号：US15371293

申请日：2016-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  Chu-Yung Liu ,  I-Chen Yang ,  Hsin-Wen Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L27/112

CPC classification number: H01L29/7838 ,  H01L27/11286 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

公开(公告)号：US09208892B2

公开(公告)日：2015-12-08

申请号：US13943691

申请日：2013-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang ,  Tao-Cheng Lu

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0475 ,  G11C16/3422

Abstract: An operation method of a multi-level memory is provided. A first read voltage lower than a standard read voltage is applied to a doped region in a substrate at one side of a control gate of the memory, so as to determine whether a first storage position and a second storage position are both at the lowest level.

Abstract translation: 提供了多级存储器的操作方法。 将低于标准读取电压的第一读取电压施加到存储器的控制栅极的一侧的衬底中的掺杂区域，以便确定第一存储位置和第二存储位置是否都处于最低级 。

公开(公告)号：US12002522B2

公开(公告)日：2024-06-04

申请号：US17743493

申请日：2022-05-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Tao-Yuan Lin ,  I-Chen Yang ,  Yao-Wen Chang

IPC: G11C16/00 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C16/10

Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.

公开(公告)号：US20240105239A1

公开(公告)日：2024-03-28

申请号：US17953094

申请日：2022-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Jung-Chuan Ting ,  I-Chen Yang

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

CPC classification number: G11C7/1057 ,  G11C7/067 ,  G11C7/12

Abstract: A memory device having a switching device for a page buffer is provided, and includes a plurality of switching units coupled between a memory cell array and a sense amplification circuit of the page buffer. Each of the plurality of switching units further comprising: a high voltage element and a low voltage element that are connected in series to each other. A first end of the high voltage element is coupled to the sense amplification circuit, and a first end of the low voltage element is coupled to a common source line of the memory cell array. A second end of the high voltage element and a second end of the low voltage element are connected to each other and coupled to a corresponding bit line of the memory cell array. The common source line coupled to each of the plurality of switching units shares a common active region.

公开(公告)号：US11177000B2

公开(公告)日：2021-11-16

申请号：US16445362

申请日：2019-06-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  Chih-Chieh Cheng ,  I-Chen Yang

IPC: G11C16/10 ,  H01L27/1157 ,  G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34

Abstract: An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period.

公开(公告)号：US10763273B2

公开(公告)日：2020-09-01

申请号：US16110897

申请日：2018-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11565 ,  G11C16/26

Abstract: A memory device comprises an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor. The array comprises a plurality of stacks of conductive lines, a stack of conductive lines including a select gate line and a word line adjacent the select gate line. The device comprises an array of vertical channel lines disposed through the conductive lines to a reference line, gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors in the array of vertical channel lines and the select gate lines, charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors in the array of vertical channel lines and the word lines, and bit lines coupled to the vertical channel lines via upper ends of the vertical channel lines.

公开(公告)号：US20200066741A1

公开(公告)日：2020-02-27

申请号：US16110897

申请日：2018-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Wei Wu ,  Yao-Wen Chang ,  I-Chen Yang

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/14

Abstract: A memory device comprises an array of two-transistor memory cells, two-transistor memory cells in the array including a vertical select transistor and a vertical data storage transistor. The array comprises a plurality of stacks of conductive lines, a stack of conductive lines including a select gate line and a word line adjacent the select gate line. The device comprises an array of vertical channel lines disposed through the conductive lines to a reference line, gate dielectric structures surrounding the vertical channel lines at channel regions of vertical select transistors in the array of vertical channel lines and the select gate lines, charge storage structures surrounding the vertical channel lines at channel regions of vertical data storage transistors in the array of vertical channel lines and the word lines, and bit lines coupled to the vertical channel lines via upper ends of the vertical channel lines.

公开(公告)号：US09978457B1

公开(公告)日：2018-05-22

申请号：US15358300

申请日：2016-11-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  I-Chen Yang

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3422

Abstract: A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias and the third bias are different.