公开(公告)号：US20190122735A1

公开(公告)日：2019-04-25

申请号：US15793045

申请日：2017-10-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/08 ,  G11C16/14 ,  G11C16/12 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/24 ,  G11C16/32

Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.

公开(公告)号：USRE46970E1

公开(公告)日：2018-07-24

申请号：US15207201

申请日：2016-07-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC: G11C17/06 ,  G11C17/16 ,  H01L21/822 ,  H01L27/10 ,  H01L27/06

CPC classification number: G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

公开(公告)号：US12112803B2

公开(公告)日：2024-10-08

申请号：US18090499

申请日：2022-12-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/08 ,  G11C16/28

CPC classification number: G11C16/08 ,  G11C16/28

Abstract: A memory device and programming method thereof are provided. A memory cell array includes a first dummy word line set, plural word lines and a second dummy word line set in sequence. The method includes: grouping the word lines into word line groups; generating at least one pass bias set having plural pass biases that are respectively corresponding to each word line group; selecting one word line for programming, and determining that the selected word line belongs to a specific word line group; and according to a programming sequence, applying a corresponding pass bias in the plural pass biases of the at least one pass bias set to at least one dummy word line in one of the first and the second dummy word line sets, wherein the corresponding pass bias corresponds to the specific word line group.

公开(公告)号：US12040024B2

公开(公告)日：2024-07-16

申请号：US17493475

申请日：2021-10-04

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory and an erase method thereof are provided. The flash memory includes at least a memory array and a memory control circuit. The memory control circuit biases plural word lines, a common source line and a global bit line included in the memory array to erase plural memory cells in the flash memory. The method comprises grouping the plural word lines into plural word line groups according to erase depths corresponding to each word line; generating an erase voltage and plural multiple-step word line erase voltages; applying the erase voltage from at least one of the common source line and the global bit line; and during a period when the erase voltage is applied, the plural multiple-step word line erase voltages is respectively applied to the plural word line groups, wherein the plural multiple-step word line erase voltages is one-by-one corresponding to the plural word line groups.

公开(公告)号：US20240221835A1

公开(公告)日：2024-07-04

申请号：US18090499

申请日：2022-12-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/08 ,  G11C16/28

CPC classification number: G11C16/08 ,  G11C16/28

Abstract: A memory device and programming method thereof are provided. A memory cell array includes a first dummy word line set, plural word lines and a second dummy word line set in sequence. The method includes: grouping the word lines into word line groups; generating at least one pass bias set having plural pass biases that are respectively corresponding to each word line group; selecting one word line for programming, and determining that the selected word line belongs to a specific word line group; and according to a programming sequence, applying a corresponding pass bias in the plural pass biases of the at least one pass bias set to at least one dummy word line in one of the first and the second dummy word line sets, wherein the corresponding pass bias corresponds to the specific word line group.

公开(公告)号：US10665303B1

公开(公告)日：2020-05-26

申请号：US16409470

申请日：2019-05-10

Applicant: Macronix International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems and apparatus for effectively erasing blocks with few programmed pages are provided. In one aspect, a system includes a memory and a controller coupled to the memory. The memory includes blocks each having pages. The controller is configured to determine whether a threshold page with a particular page number in a block of the memory is programmed, to erase the block according to a normal erase action in response to determining that the threshold page is programmed, and to erase the block according to a particular erasing action that is configured to erase the block deeper than the normal erase action in response to determining that the threshold page is not programmed. The particular erasing action can include pre-programming the block before erasing the block, decreasing an erase verify voltage before erasing the block, or adding one or more erasing pulses with a new erasing voltage.

公开(公告)号：US09613702B1

公开(公告)日：2017-04-04

申请号：US14986124

申请日：2015-12-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C11/34 ,  G11C16/08 ,  G11C11/418 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C5/05 ,  G11C5/063 ,  G11C11/418 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/24 ,  H01L27/11519 ,  H01L27/11524

Abstract: A memory device including multiple word lines, multiple bit lines and a memory cell array is provided. The word lines intersect the bit lines, and an included angle between the word lines and the bit lines is not a right angle. The memory cell array includes multiple memory cells respectively disposed at the intersections of the word lines and the bit lines. Each row of the memory cells is electrically connected to one of the word lines, and each column of the memory cells is electrically connected to one of the bit lines.

公开(公告)号：US20140050006A1

公开(公告)日：2014-02-20

申请号：US14063284

申请日：2013-10-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming-Shang Chen

IPC: G11C17/16

CPC classification number: G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract translation: 一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体 并且设置成与第一行导体相邻并且与第二行导体相邻。 阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。