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公开(公告)号：US20170344300A1
公开(公告)日：2017-11-30
申请号：US15370059
申请日：2016-12-06
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yuan-Hao Chang , Hsiu-Chang Chen , Tei-Wei Kuo
IPC: G06F3/06
CPC classification number: G06F12/121 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/1009 , G06F2212/1016 , G06F2212/205 , G06F2212/7208
Abstract: A memory management method includes: providing a hybrid memory comprising a first type memory and a second type memory; providing an inactive list and a read active list for recording in-used pages on the first type memory; providing a write active list for recording in-used pages on the second type memory; allocating a page from the first type memory according to a system request, and inserting the page into the inactive list accordingly; moving the page from the inactive list to the write active list or the read active list in response to two or more successive access operations on the page; and referring the page to a physical address on the second type memory when the page is in the write active list.
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公开(公告)号：US20170148493A1
公开(公告)日：2017-05-25
申请号：US15212340
申请日：2016-07-18
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hsin-Yu Chang , Chien-Chung Ho , Yuan-Hao Chang
IPC: G11C7/00
Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.
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公开(公告)号：US09558108B2
公开(公告)日：2017-01-31
申请号：US14018149
申请日：2013-09-04
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Hsing-Chen Lu , Hsiang-Pang Li , Cheng-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G06F12/0246 , G06F2212/7205 , G11C16/0483 , G11C16/16 , G11C16/3427
Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.
Abstract translation: 提供了一种用于管理块擦除操作的方法，用于包括阵列中的可擦除存储单元块的存储单元阵列。 该方法包括维护阵列的可擦除块的多个子块的状态数据。 状态数据指示子块当前是否可访问以及子块是否无效。 该方法响应于擦除特定可擦除块的所选子块的请求，如果特定可擦除块的其他子块无效则发出擦除命令以擦除特定块，否则更新状态数据 以指示所选择的子块是无效的。
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公开(公告)号：US20160300617A1
公开(公告)日：2016-10-13
申请号：US14684561
申请日：2015-04-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hung-Sheng Chang , Chih-Chang Hsieh , Kuo-Pin Chang
IPC: G11C16/16
Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.
Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。
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公开(公告)号：US09466384B1
公开(公告)日：2016-10-11
申请号：US14684561
申请日：2015-04-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hung-Sheng Chang , Chih-Chang Hsieh , Kuo-Pin Chang
Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.
Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。
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Patent Agency Ranking
公开(公告)号：US20160155516A1
公开(公告)日：2016-06-02
申请号：US14824192
申请日：2015-08-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Tai-Chun Kuo , Wei-Chieh Huang , Ping-Hsien Lin , Tzu-Hsiang Su
CPC classification number: G06F12/023 , G06F19/00 , G06F2212/1032 , G11C16/349
Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.
Abstract translation: 提供了一种用于存储器件的读取调平方法。 存储器件包括第一存储器块和至少第二存储器块。 读取调平方法包括以下步骤。 确定第一存储块的块读取计数是否大于或等于第一阈值。 当第一存储器块的块读取计数大于或等于第一阈值时，检测第一存储器块的页面的页面读取计数。 确定第一存储块的块读取计数是否大于或等于第二阈值。 当第一存储器块的块读取计数大于或等于第二阈值时，将第一存储器块的页面之一的数据移动到第二存储器块的页面。
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公开(公告)号：US09348748B2
公开(公告)日：2016-05-24
申请号：US14578820
申请日：2014-12-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hang-Ting Lue , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G06F12/0246 , G06F12/00 , G06F2212/1036 , G06F2212/7211 , G11C16/3495 , G11C29/4401
Abstract: Technology is described that increases endurance of memory devices through heal leveling. Heal leveling is a lightweight solution to distribute healing cycles among memory blocks. Approaches described herein can accomplish heal leveling without introducing a large amount of overhead. Heal leveling significantly improves the access performance and the effective lifetime of memory blocks. By more evenly distributing the heal count it may not be necessary to directly apply wear leveling based on access counts of each block because each block will be more evenly accessed in the long run. Heal leveling may be performed by moving data that is seldom or never modified after creation, such as read-only files, to blocks having suffered the greatest number, or a high number, of healing cycles.
Abstract translation: 技术被描述为通过愈合平整来增加记忆装置的耐久性。 治疗矫正是一种轻量级的解决方案，可以在内存块之间分配愈合周期。 本文描述的方法可以在不引入大量开销的情况下完成愈合平整。 愈合程度显着提高了存储块的访问性能和有效寿命。 通过更均匀地分配治疗计数，可能不需要基于每个块的访问计数来直接应用磨损均衡，因为长期来看每个块将被更均匀地访问。 可以通过将创建后很少或从不修改的数据（例如只读文件）移动到遭受最大数量的块或大量愈合周期来执行愈合调平。
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公开(公告)号：US09305638B1
公开(公告)日：2016-04-05
申请号：US14526560
申请日：2014-10-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Chih-Chang Hsieh , Shih-Fu Huang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G11C11/5628 , G11C7/1006 , G11C11/5642 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.
Abstract translation: 提供了存储器件的操作方法。 存储器件的操作方法包括如下所述对存储器件进行编程。 提供数据。 数据包括多个代码。 每个代码数都被计数。 然后，根据代码的数量生成映射规则。 在映射规则中，每个代码被映射到从低到高顺序排列的多个验证电压电平之一。 之后，根据映射规则将数据编程到存储设备中。
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公开(公告)号：US09760478B2
公开(公告)日：2017-09-12
申请号：US14824192
申请日：2015-08-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Tai-Chun Kuo , Wei-Chieh Huang , Ping-Hsien Lin , Tzu-Hsiang Su
CPC classification number: G06F12/023 , G06F19/00 , G06F2212/1032 , G11C16/349
Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.
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公开(公告)号：US09734912B2
公开(公告)日：2017-08-15
申请号：US15208175
申请日：2016-07-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Yu-Ming Chang , Ping-Hsien Lin , Hsiang-Pang Li
CPC classification number: G11C16/10 , G11C7/14 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0466 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C16/349 , G11C16/3495 , G11C2211/5634 , G11C2211/5641
Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.
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