-
1.发明授权公开(公告)号：US11194515B2
公开(公告)日：2021-12-07
申请号：US16571249
申请日：2019-09-16
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ping-Hsien Lin , Wei-Chen Wang , Hsiang-Pang Li , Shu-Hsien Liao , Che-Wei Tsao , Yuan-Hao Chang , Tei-Wei Kuo
Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.
-
公开(公告)号：US20200319803A1
公开(公告)日：2020-10-08
申请号：US16742811
申请日：2020-01-14
Applicant: MACRONIX International Co., Ltd.
Inventor： Wei-Chen Wang , Ping-Hsien Lin , Tse-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F3/06 , G06F16/901 , G06F12/10
Abstract: A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.
-
公开(公告)号：US10445008B2
公开(公告)日：2019-10-15
申请号：US15705309
申请日：2017-09-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Ping-Hsien Lin , Yu-Ming Chang
Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.
-
公开(公告)号：US20160155516A1
公开(公告)日：2016-06-02
申请号：US14824192
申请日：2015-08-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Tai-Chun Kuo , Wei-Chieh Huang , Ping-Hsien Lin , Tzu-Hsiang Su
CPC classification number: G06F12/023 , G06F19/00 , G06F2212/1032 , G11C16/349
Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.
Abstract translation: 提供了一种用于存储器件的读取调平方法。 存储器件包括第一存储器块和至少第二存储器块。 读取调平方法包括以下步骤。 确定第一存储块的块读取计数是否大于或等于第一阈值。 当第一存储器块的块读取计数大于或等于第一阈值时，检测第一存储器块的页面的页面读取计数。 确定第一存储块的块读取计数是否大于或等于第二阈值。 当第一存储器块的块读取计数大于或等于第二阈值时，将第一存储器块的页面之一的数据移动到第二存储器块的页面。
-
公开(公告)号：US11042308B2
公开(公告)日：2021-06-22
申请号：US16742811
申请日：2020-01-14
Applicant: MACRONIX International Co., Ltd.
Inventor： Wei-Chen Wang , Ping-Hsien Lin , Tse-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F3/06 , G06F16/901 , G06F12/10
Abstract: A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.
-
Patent Agency Ranking
公开(公告)号：US11010244B2
公开(公告)日：2021-05-18
申请号：US16571260
申请日：2019-09-16
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Ping-Hsien Lin , Kun-Chi Chiang , Chien-Chung Ho
IPC: G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , G06F11/10 , G06F11/07 , G11C11/4074 , G11C11/409
Abstract: A memory data management method includes the following steps reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to increase a first threshold voltage of a first state data of the data for exceeding a first threshold, to increase a second threshold voltage of a second state data of the data for exceeding a second threshold, and to increase a third threshold voltage of a third state data of the data for exceeding a third threshold.
-
公开(公告)号：US09760478B2
公开(公告)日：2017-09-12
申请号：US14824192
申请日：2015-08-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Tai-Chun Kuo , Wei-Chieh Huang , Ping-Hsien Lin , Tzu-Hsiang Su
CPC classification number: G06F12/023 , G06F19/00 , G06F2212/1032 , G11C16/349
Abstract: A read leveling method for a memory device is provided. The memory device includes a first memory block and at least a second memory block. The read leveling method includes the following steps. Determining whether a block read count of the first memory block is larger than or equal to a first threshold. Detecting a page read count of a page of the first memory block when the block read count of the first memory block is larger than or equal to the first threshold. Determine whether the block read count of the first memory block is larger than or equal to a second threshold. Move data of one of the page of the first memory block to a page of the second memory block when the block read count of the first memory block is larger than or equal to the second threshold.
-
公开(公告)号：US09734912B2
公开(公告)日：2017-08-15
申请号：US15208175
申请日：2016-07-12
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Yu-Ming Chang , Ping-Hsien Lin , Hsiang-Pang Li
CPC classification number: G11C16/10 , G11C7/14 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0466 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C16/349 , G11C16/3495 , G11C2211/5634 , G11C2211/5641
Abstract: A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.
-
公开(公告)号：US10748605B2
公开(公告)日：2020-08-18
申请号：US16057871
申请日：2018-08-08
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Ping-Hsien Lin
Abstract: Provided is a programming method for a memory device including a memory array and a controller. The programming method including: controlling programming on a first page of a first word line by the controller; controlling programming on a first page of a second word line by the controller, the second word line being adjacent to the first word line; controlling for performing a first programming operation on a second page of the first word line by the controller; controlling programming on a first page of a third word line by the controller, the third word line being adjacent to the second word line; controlling for performing the first programming operation on a second page of the second word line by the controller; and controlling for performing a second programming operation on the second page of the first word line by the controller.
-
公开(公告)号：US20190087110A1
公开(公告)日：2019-03-21
申请号：US15705309
申请日：2017-09-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Ping-Hsien Lin , Yu-Ming Chang
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0634 , G06F3/0655 , G06F3/0688 , G11C11/5628 , G11C16/08 , G11C16/10 , G11C16/3418
Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.014 seconds)
