公开(公告)号：US10127169B2

公开(公告)日：2018-11-13

申请号：US15043622

申请日：2016-02-15

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su

IPC: G06F13/16 ,  H01L23/498 ,  G06F13/368 ,  G06F13/40 ,  H01L25/065

Abstract: A semiconductor die assembled in a wafer-level package includes a communication interface and a bus master. The bus master is coupled to a communication bus through the communication interface. The bus master communicates with a bus slave of another semiconductor die assembled in the wafer-level package via the communication bus, and is controlled by a flow control mechanism that manages a transaction flow initiated by the bus master over the communication bus.

公开(公告)号：US09852101B2

公开(公告)日：2017-12-26

申请号：US14583206

申请日：2014-12-26

Applicant: MEDIATEK INC.

Inventor： Shin-Shiun Chen ,  Chen-Hao Chang ,  Hong-Ching Chen ,  Yao-Chun Su

IPC: G06F13/00 ,  G06F3/00 ,  G06F12/00 ,  G06F13/28 ,  G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4221 ,  G06F13/364

Abstract: An electronic device has a management data input/output (MDIO) bus, a control unit, and an MDIO master. The control circuit receives a host command from a host device, and outputs a plurality of MDIO commands in response to the host command. The MDIO master receives the MDIO commands from the control circuit, and transmits the MDIO commands to the MDIO bus.

公开(公告)号：US20170054656A1

公开(公告)日：2017-02-23

申请号：US15050473

申请日：2016-02-23

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Hao-Hui Yin ,  Chih-Ching Yu ,  Yao-Chun Su

IPC: H04L12/931 ,  H04L12/935

CPC classification number: H04L49/40 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311 ,  H03M9/00 ,  H04L49/30

Abstract: A multi-chip structure comprises a switch system on chip (switch SOC), a plurality of serializer/deserializer (SerDes) chips positioned around the switch SOC, and a plurality of inter-chip interfaces for connecting the switch SOC to the plurality of SerDes chips, respectively.

Abstract translation: 多芯片结构包括片上开关系统（开关SOC），位于开关SOC周围的多个串行器/解串器（SerDes）芯片，以及用于将开关SOC连接到多个SerDes的多个芯片间接口 芯片。

公开(公告)号：US20160240507A1

公开(公告)日：2016-08-18

申请号：US15043611

申请日：2016-02-14

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su

IPC: H01L25/065 ,  H01L23/498

CPC classification number: G06F13/368 ,  G06F13/4068 ,  H01L23/49811 ,  H01L23/49838 ,  H01L25/065 ,  H01L2225/06506 ,  H01L2225/06527

Abstract: A wafer-level package has a first input/output (I/O) port, a second I/O port, a first semiconductor die, and a second semiconductor die. The first I/O port and the second I/O port of the wafer-level package are arranged to connect at least one management bus. The first semiconductor die and the second semiconductor die assembled in the wafer-level package are arranged to receive commands from the first I/O port and the second I/O port, respectively.

Abstract translation: 晶片级封装具有第一输入/输出（I / O）端口，第二I / O端口，第一半导体管芯和第二半导体管芯。 晶片级封装的第一I / O端口和第二I / O端口被布置成连接至少一个管理总线。 组装在晶片级封装中的第一半导体管芯和第二半导体管芯分别布置成从第一I / O端口和第二I / O端口接收命令。

公开(公告)号：US20240055358A1

公开(公告)日：2024-02-15

申请号：US18383466

申请日：2023-10-24

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.

公开(公告)号：US11830820B2

公开(公告)日：2023-11-28

申请号：US17553760

申请日：2021-12-16

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6638 ,  H01L2223/6666

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

公开(公告)号：US11508707B2

公开(公告)日：2022-11-22

申请号：US16869574

申请日：2020-05-07

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Ching Chen ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

公开(公告)号：US20220108954A1

公开(公告)日：2022-04-07

申请号：US17553760

申请日：2021-12-16

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su ,  Chih-Jung Hsu ,  Yi-Jou Lin ,  I-Hsuan Peng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H01L25/065

Abstract: An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.

公开(公告)号：US10397142B2

公开(公告)日：2019-08-27

申请号：US15050473

申请日：2016-02-23

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Hao-Hui Yin ,  Chih-Ching Yu ,  Yao-Chun Su

IPC: H03M9/00 ,  H04L12/931 ,  H04L12/935 ,  H01L25/065 ,  H01L25/18

Abstract: A multi-chip structure comprises a switch system on chip (switch SOC), a plurality of serializer/deserializer (SerDes) chips positioned around the switch SOC, and a plurality of inter-chip interfaces for connecting the switch SOC to the plurality of SerDes chips, respectively.

公开(公告)号：US20160239452A1

公开(公告)日：2016-08-18

申请号：US15009819

申请日：2016-01-28

Applicant: MEDIATEK INC.

Inventor： Yao-Chun Su

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/3625 ,  G06F13/364 ,  G06F13/4282 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/24137

Abstract: A semiconductor die assembled in a wafer-level package includes a processing circuit, a multiplexer, and a transmit interface. The processing circuit generates a plurality of signal outputs. The multiplexer multiplexes the signal outputs into a multiplexed signal. The transmit interface transmits the multiplexed signal to another semiconductor die assembled in the wafer-level package.

Abstract translation: 组装在晶片级封装中的半导体管芯包括处理电路，多路复用器和发送接口。 处理电路产生多个信号输出。 多路复用器将信号输出复用为复用信号。 发送接口将复用的信号发送到晶片级封装中组装的另一个半导体管芯。