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公开(公告)号:US20210168935A1
公开(公告)日:2021-06-03
申请号:US17092312
申请日:2020-11-08
Applicant: MEDIATEK INC.
Inventor: Yi-Chieh Lin
IPC: H05K1/11 , H01L23/498 , H01L23/66
Abstract: A vertical interconnection structure of a multi-layer substrate includes a first via pad disposed in a first layer of metal interconnect of the multi-layer substrate; a second via pad disposed in a second layer of metal interconnect of the multi-layer substrate; a signal via electrically connecting the first via pad to the second via pad; a non-circular first ground plane disposed in the first layer of metal interconnect of the multi-layer substrate and surrounding the first via pad; and a non-circular first ground pullback region between the first via pad and the non-circular first ground plane for electrically isolating the first via pad from the non-circular first ground plane.
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公开(公告)号:US20200303806A1
公开(公告)日:2020-09-24
申请号:US16867583
申请日:2020-05-06
Applicant: MEDIATEK INC.
Inventor: Wen-Chou Wu , Yi-Chieh Lin , Chia-Yu Jin , Hsing-Chih Liu
IPC: H01Q1/22 , H01L23/498 , H01L25/16 , H01Q21/06
Abstract: A semiconductor package includes a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A connector is disposed on the second side.
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公开(公告)号:US20250015483A1
公开(公告)日:2025-01-09
申请号:US18885764
申请日:2024-09-16
Applicant: MEDIATEK INC.
Inventor: Wen-Chou Wu , Yi-Chieh Lin , Chia-Yu Jin , Hsing-Chih Liu
IPC: H01Q1/22 , H01L23/498 , H01L25/16 , H01Q21/06
Abstract: A semiconductor package includes a first package having a first side and a second side opposing the first side. The first package comprises a first electronic component and a second electronic component arranged in a side-by-side manner on the second side. A second package is mounted on the first side of the first package. The second package comprises a radiative antenna element. A connector is configured to electrically couple to a 5G modem through a flex cable and is disposed on the second side.
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公开(公告)号:US12095142B2
公开(公告)日:2024-09-17
申请号:US17965787
申请日:2022-10-14
Applicant: MEDIATEK INC.
Inventor: Wen-Chou Wu , Yi-Chieh Lin , Chia-Yu Jin , Hsing-Chih Liu
IPC: H01Q1/22 , H01L23/498 , H01L25/16 , H01Q21/06
CPC classification number: H01Q1/2283 , H01L23/49816 , H01L23/49838 , H01L25/16 , H01Q21/06
Abstract: A semiconductor package includes a first package having a first side and a second side opposing the first side. The first package comprises a first electronic component and a second electronic component arranged in a side-by-side manner on the second side. A second package is mounted on the first side of the first package. The second package comprises a radiative antenna element. A connector is disposed on the second side.
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公开(公告)号:US11864315B2
公开(公告)日:2024-01-02
申请号:US17092312
申请日:2020-11-08
Applicant: MEDIATEK INC.
Inventor: Yi-Chieh Lin
IPC: H05K1/11 , H05K1/02 , H01L23/498 , H01L23/66
CPC classification number: H05K1/113 , H01L23/49822 , H01L23/66 , H05K1/0222 , H05K1/0224 , H01L2223/6616 , H05K1/115 , H05K2201/093 , H05K2201/10098
Abstract: A vertical interconnection structure of a multi-layer substrate includes a first via pad disposed in a first layer of metal interconnect of the multi-layer substrate; a second via pad disposed in a second layer of metal interconnect of the multi-layer substrate; a signal via electrically connecting the first via pad to the second via pad; a non-circular first ground plane disposed in the first layer of metal interconnect of the multi-layer substrate and surrounding the first via pad; and a non-circular first ground pullback region between the first via pad and the non-circular first ground plane for electrically isolating the first via pad from the non-circular first ground plane.
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公开(公告)号:US20220397600A1
公开(公告)日:2022-12-15
申请号:US17735130
申请日:2022-05-03
Applicant: MEDIATEK INC.
Inventor: Jing-Hui Zhuang , Ying-Chou Shih , Sheng-Wei Lei , Chang-Lin Wei , Chih-Yang Liu , Che-Hsien Huang , Yi-Chieh Lin
Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.
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公开(公告)号:US11509038B2
公开(公告)日:2022-11-22
申请号:US16867583
申请日:2020-05-06
Applicant: MEDIATEK INC.
Inventor: Wen-Chou Wu , Yi-Chieh Lin , Chia-Yu Jin , Hsing-Chih Liu
IPC: H01Q1/22 , H01L23/498 , H01Q21/06 , H01L25/16
Abstract: A semiconductor package includes a bottom chip package having a first side and a second side opposing the first side. The bottom chip package comprises a first semiconductor chip and a second semiconductor chip arranged in a side-by-side manner on the second side. A top antenna package is mounted on the first side of the bottom chip package. The top antenna package comprises a radiative antenna element. A connector is disposed on the second side.
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公开(公告)号:US20210057143A1
公开(公告)日:2021-02-25
申请号:US16940379
申请日:2020-07-27
Applicant: MEDIATEK INC.
Inventor: Yi-Chieh Lin , Shih-Chia Chiu
Abstract: A filter circuit includes an input node, an output node, a first filtering element and a second filtering element. The first filtering element has a first terminal coupled to the input node and a second terminal, and is configured to provide a first signal conducting path toward the second terminal for conducting a first signal received at the input node to the second terminal. The second filtering element has a first terminal coupled to the input node and a second terminal, and is configured to provide a second signal conducting path toward the output node for conducting a second signal received at the input node to the output node. The second terminal of the first filtering element and the second terminal of the second filtering element are open-circuit terminals.
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公开(公告)号:US20200051927A1
公开(公告)日:2020-02-13
申请号:US16539808
申请日:2019-08-13
Applicant: MediaTek Inc.
Inventor: Yi-Chieh Lin , Sheng-Mou Lin , Wen-Chou Wu
IPC: H01L23/552 , H05K1/02 , H01L23/00 , H01L23/498
Abstract: A semiconductor device includes a first layer structure, a first layer structure, a second layer structure and a passive electronic component. The second layer structure is disposed below the first layer structure and coupled to a ground. The conductive structure is coupled to the first layer structure. The conductive structure is installed vertically between the first layer structure and the second layer structure, and is coupled to a first pad of the second layer structure. The passive electronic component comprises a first terminal coupled to the first pad of the second layer structure and a second terminal coupled to a second pad of the second layer structure. The conductive structure and the passive electronic component are connected in series between the first layer structure and the ground to form a conductive path for conducting at least one electromagnetic interference signal to the ground.
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