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    RATIONAL VALUE RATE LIMITER
    11.
    发明公开
    RATIONAL VALUE RATE LIMITER 审中-公开

    公开(公告)号：US20230362084A1

    公开(公告)日：2023-11-09

    申请号：US18106933

    申请日：2023-02-07

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Alex Vainman ,  Roee Moyal

    IPC: H04L43/0888

    CPC classification number: H04L43/0888

    Abstract: A system includes a device configured to execute workloads coupled to a processing device. The processing device is to receive a request to execute one or more workloads, the request comprising two or more numbers corresponding to a rational value associated with a rate to execute the one or more workloads. The processing device is further to determine the rate to execute the one or more workloads responsive to receiving the two or more numbers corresponding to the rational values. The processing device is to execute the one or more workloads at the determined rate.

    SYNCHRONIZED RATE CONTROL AT RATE LIMITER
    12.
    发明公开
    SYNCHRONIZED RATE CONTROL AT RATE LIMITER 审中-公开

    公开(公告)号：US20230361900A1

    公开(公告)日：2023-11-09

    申请号：US18107442

    申请日：2023-02-08

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Dotan David Levi ,  Liron Mula ,  Natan Manevich

    IPC: H04J3/06 ,  H04L47/25

    CPC classification number: H04J3/0652 ,  H04L47/25 ,  H04J3/0667

    Abstract: A system includes a device coupled to a processing device. The processing device is to receive a timing signal associated with a synchronized time. The processing device is further to synchronize a rate limiter of the device to the synchronized time responsive to receiving the timing signal, wherein the rate limiter is configured to schedule one or more workloads at a respective rate. The processing device is to receive a request to execute the one or more workloads, the request comprising a rate to execute each workload of the one or more workloads. The processing device is to execute the one or more workloads at the respective rate upon synchronizing the rate limiter.

    Hardware Clock with Built-In Accuracy Check
    18.
    发明申请
    Hardware Clock with Built-In Accuracy Check 有权

    公开(公告)号：US20220224500A1

    公开(公告)日：2022-07-14

    申请号：US17148605

    申请日：2021-01-14

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Dotan David Levi ,  Ariel Almog

    IPC: H04L7/00

    Abstract: A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

    Synthesized clock synchronization between network devices
    19.
    发明授权
    Synthesized clock synchronization between network devices 有权

    公开(公告)号：US11283454B2

    公开(公告)日：2022-03-22

    申请号：US16920772

    申请日：2020-07-06

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ran Ravid ,  Aviv Berg ,  Lavi Koch ,  Chen Gaist ,  Dotan David Levi

    IPC: H03L7/08 ,  G06F1/12 ,  H04L7/033 ,  H03L7/099

    Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

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