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公开(公告)号：US11336383B2
公开(公告)日：2022-05-17
申请号：US16910193
申请日：2020-06-24
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Liron Mula , Dotan David Levi , Ran Ravid , Guy Lederman
IPC: H04J3/06 , H04L12/46 , H04L43/0852 , H04L69/22
Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.
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公开(公告)号：US20200169379A1
公开(公告)日：2020-05-28
申请号：US16199312
申请日：2018-11-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Chen Gaist , Ran Ravid , Aviv Berg , Lavi Koch
IPC: H04L7/04
Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US09344117B2
公开(公告)日：2016-05-17
申请号：US13839193
申请日：2013-03-15
Applicant: Mellanox Technologies Ltd.
Inventor： Liron Mula , Ran Ravid , Chen Gaist , Omer Sella , Oren Tzvi Sela
CPC classification number: H03M13/1515 , H03M13/153 , H03M13/1575 , H03M13/3715
Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.
Abstract translation: 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。
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公开(公告)号：US10778406B2
公开(公告)日：2020-09-15
申请号：US16199312
申请日：2018-11-26
Applicant: Mellanox Technologies, Ltd.
Inventor： Chen Gaist , Ran Ravid , Aviv Berg , Lavi Koch
IPC: H04L7/04
Abstract: A network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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公开(公告)号：US09584429B2
公开(公告)日：2017-02-28
申请号：US14335962
申请日：2014-07-21
Applicant: Mellanox Technologies Ltd.
Inventor： Zachy Haramaty , Roy Kriss , Noam Katz Abramovich , George Elias , Ran Ravid
IPC: H04L12/801 , H04L12/807 , H04L12/863 , H04L12/825 , H04L12/835
CPC classification number: H04L47/39 , H04L47/263 , H04L47/30
Abstract: A method for communication includes storing packets received from a sending node over a communication link in a receive buffer of a receiving node. The receive buffer includes one or more blocks having a first block size. A first credit count, corresponding to a number of available blocks in the receive buffer, is derived. The first credit count is converted to a second credit count so as to represent an available space in the receive buffer in accordance with a second block size, which is different from the first block size. A transmission rate of the sending node is controlled by publishing the second credit count to the sending node over the communication link.
Abstract translation: 一种用于通信的方法包括：通过接收节点的接收缓冲器中的通信链路存储从发送节点接收的分组。 接收缓冲器包括具有第一块大小的一个或多个块。 导出与接收缓冲器中的多个可用块相对应的第一信用计数。 第一信用计数被转换为第二信用计数，以便根据与第一块大小不同的第二块大小表示接收缓冲器中的可用空间。 发送节点的传输速率通过通过通信链路向发送节点发布第二信用计数来控制。
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Patent Agency Ranking
公开(公告)号：US20160021016A1
公开(公告)日：2016-01-21
申请号：US14335962
申请日：2014-07-21
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Zachy Haramaty , Roy Kriss , Noam Katz Abramovich , George Elias , Ran Ravid
IPC: H04L12/807 , H04L12/863 , H04L12/801
CPC classification number: H04L47/39 , H04L47/263 , H04L47/30
Abstract: A method for communication includes storing packets received from a sending node over a communication link in a receive buffer of a receiving node. The receive buffer includes one or more blocks having a first block size. A first credit count, corresponding to a number of available blocks in the receive buffer, is derived. The first credit count is converted to a second credit count so as to represent an available space in the receive buffer in accordance with a second block size, which is different from the first block size. A transmission rate of the sending node is controlled by publishing the second credit count to the sending node over the communication link.
Abstract translation: 一种用于通信的方法包括：通过接收节点的接收缓冲器中的通信链路存储从发送节点接收的分组。 接收缓冲器包括具有第一块大小的一个或多个块。 导出与接收缓冲器中的多个可用块相对应的第一信用计数。 第一信用计数被转换为第二信用计数，以便根据与第一块大小不同的第二块大小表示接收缓冲器中的可用空间。 发送节点的传输速率通过通过通信链路向发送节点发布第二信用计数来控制。
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公开(公告)号：US20140281840A1
公开(公告)日：2014-09-18
申请号：US13839193
申请日：2013-03-15
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Liron Mula , Ran Ravid , Chen Gaist , Omer Sela , Oren Tzvi Sela
IPC: H03M13/15
CPC classification number: H03M13/1515 , H03M13/153 , H03M13/1575 , H03M13/3715
Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.
Abstract translation: 提供了有效的里德 - 所罗门（RS）解码的方法和系统。 RS解码单元包括RS伪解码器和RS解码器。 RS伪解码器被配置为校正接收到的码字中的少量错误，而RS解码器被配置为校正可由RS码恢复的错误。 RS伪解码器与RS解码器并行运行。 一旦RS伪解码器成功解码码字，则RS解码器可能停止其处理，从而降低RS解码延迟。
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公开(公告)号：US20140269711A1
公开(公告)日：2014-09-18
申请号：US13802926
申请日：2013-03-14
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor： Ran Ravid , Zachy Haramaty , Roy Kriss , Oded Wertheim
IPC: H04L12/747 , H04L12/879
CPC classification number: H04L45/742 , H04L47/125 , H04L47/30 , H04L47/39
Abstract: A method for communication includes, in a sender node that sends packets to a receiver node over a physical link, making a decision, for a packet that is associated with a respective virtual link selected from among multiple virtual links, whether the receiver node is to buffer the packet in a dedicated buffer assigned to the respective virtual link or in a shared buffer that is shared among the multiple virtual links. The packet is sent, and the decision is signaled, from the sender node to the receiver node.
Abstract translation: 一种用于通信的方法包括：在通过物理链路向接收方节点发送分组的发送方节点对与从多个虚拟链路中选择的相应虚拟链路相关联的分组作出决定，接收方节点是否 在分配给相应虚拟链路的专用缓冲器中或在多个虚拟链路之间共享的共享缓冲器中缓冲分组。 从发送方节点向接收方节点发送分组，并发送决定信号。
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公开(公告)号：US12244416B2
公开(公告)日：2025-03-04
申请号：US18192239
申请日：2023-03-29
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Asaf Horev , Ran Ravid , Guy Lederman , Roman Meltser
Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.
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公开(公告)号：US20220021393A1
公开(公告)日：2022-01-20
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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