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    Memory-based synchronization of distributed operations
    11.
    发明申请
    Memory-based synchronization of distributed operations 有权

    公开(公告)号：US20220398197A1

    公开(公告)日：2022-12-15

    申请号：US17863453

    申请日：2022-07-13

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Ariel Shahar ,  Roee Moyal ,  Igor Voks

    IPC: G06F12/0813 ,  G06F12/06 ,  G06F9/54 ,  G06F9/50

    Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

    Memory-based synchronization of distributed operations
    12.
    发明申请
    Memory-based synchronization of distributed operations 有权

    公开(公告)号：US20210406179A1

    公开(公告)日：2021-12-30

    申请号：US16916153

    申请日：2020-06-30

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Ariel Shahar ,  Roee Moyal ,  Igor Voks

    IPC: G06F12/0813 ,  G06F12/06 ,  G06F9/50 ,  G06F9/54

    Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

    Aggregation protocol
    13.
    发明申请
    Aggregation protocol 审中-公开
    聚合协议

    公开(公告)号：US20170063613A1

    公开(公告)日：2017-03-02

    申请号：US15250953

    申请日：2016-08-30

    Applicant: Mellanox Technologies Ltd.

    Inventor： Gil Bloch ,  Diego Crupnicoff ,  Benny Koren ,  Oded Wertheim ,  Lion Levi ,  Richard Graham ,  Michael Kagan

    IPC: H04L12/24 ,  H04L12/18 ,  H04L12/44

    CPC classification number: H04L12/185 ,  H04L12/44 ,  H04L41/12

    Abstract: A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.

    Abstract translation: 数据网络中的交换机被配置为中介网元之间的数据交换。 该装置还包括处理器，其将网络元件组织成具有根节点网络元件的分层树，顶点节点网络元素包括叶节点网络元素的子节点网络元素。 叶节点网元是始发聚合数据，并将聚合数据发送到相应的父顶点节点网元。 顶点节点网络元素组合来自至少一部分子节点网元的聚合数据，并将组合聚合数据从顶点节点网元发送到父顶点节点网元。 根节点网元可用于启动对聚合数据的简化操作。

    Direct IO access from a CPU's instruction stream
    14.
    发明申请
    Direct IO access from a CPU's instruction stream 有权
    从CPU的指令流直接访问IO

    公开(公告)号：US20150212817A1

    公开(公告)日：2015-07-30

    申请号：US14608252

    申请日：2015-01-29

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Shlomo Raikin ,  Noam Bloch ,  Richard Graham ,  Ofer Hayut ,  Michael Kagan ,  Liran Liss

    IPC: G06F9/30 ,  G06F11/22 ,  G06F11/36

    CPC classification number: G06F11/073 ,  G06F9/30043 ,  G06F11/0745 ,  G06F11/0757 ,  G06F11/2236 ,  G06F11/3668

    Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

    Abstract translation: 一种使用常规负载和存储直接从本地指令流网络访问远程存储器的方法。 在网络IO访问（网络阶段）不能与计算阶段重叠的情况下，来自指令流的直接网络访问大大降低了CPU处理中的延迟。 该网络被视为可以直接从CPU读取或写入的另一个存储器。 网络访问可以直接从指令流使用常规的负载和存储。 同步网络访问可能有益的示例场景是SHMEM（对称分层存储器访问）用途（程序直接读/写远程内存的位置）以及系统内存（例如DDR）的一部分可以驻留在网络上并使其可访问的情况 通过需求到不同的CPU。

    Network interface controller with direct connection to host memory
    19.
    发明申请
    Network interface controller with direct connection to host memory 有权
    网络接口控制器，与主机内存直接连接

    公开(公告)号：US20160283422A1

    公开(公告)日：2016-09-29

    申请号：US15181436

    申请日：2016-06-14

    Applicant: Mellanox Technologies Ltd.

    Inventor： Diego Crupnicoff ,  Todd Wilde ,  Richard Graham ,  Michael Kagan

    IPC: G06F13/28 ,  G06F13/42 ,  G11C7/10 ,  G06F13/40

    CPC classification number: G06F13/4022 ,  G06F12/0835 ,  G06F13/28 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/1072

    Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

    Abstract translation: 用于主计算机的网络接口设备包括网络接口，被配置为向网络发送数据分组和从网络接收数据分组。 分组处理逻辑通过来自主计算机的系统存储器的直接存储器访问（DMA）经由网络接口​​传送和接收的数据分组传送数据。 存储器控制器包括被配置为连接到系统存储器的第一存储器接口和被配置为连接到主计算机的主机复合体的第二存储器接口。 开关逻辑将第一存储器接口交替地耦合到DMA配置中的分组处理逻辑，并以直通配置耦合到第二存储器接口。

    HYBRID TAG MATCHING
    20.
    发明申请
    HYBRID TAG MATCHING 有权
    混合标签匹配

    公开(公告)号：US20160072906A1

    公开(公告)日：2016-03-10

    申请号：US14834443

    申请日：2015-08-25

    Applicant: Mellanox Technologies Ltd.

    Inventor： Shahaf Shuler ,  Noam Bloch ,  Ofer Hayut ,  Richard Graham ,  Ariel Shahar

    IPC: H04L29/08 ,  H04L29/06

    CPC classification number: H04L67/26 ,  H04L49/9068 ,  H04L67/10 ,  H04L67/1093 ,  H04L67/1097 ,  H04L69/06

    Abstract: A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.

    Abstract translation: 一种用于通信的方法包括通过软件处理将主机处理器的存储器中的一组缓冲器发布，并在存储器中创建分别与缓冲器相关联的标签的列表。 软件进程将列表的第一部分推送到网络接口控制器（NIC），同时在软件进程控制下将列表的第二部分保留在内存中。 在接收到包含通过网络发送的标签的消息时，NIC将标签与列表的第一部分中的标签进行比较，并且在找到与标签的匹配时，将消息传送的数据写入存储器中的缓冲器 。 如果在列表的第一部分找不到匹配项，则NIC将该消息从NIC传递到软件进程以使用列表的第二部分进行处理。

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