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    Integrated assemblies and methods of forming integrated assemblies
    11.
    发明授权
    Integrated assemblies and methods of forming integrated assemblies 有权

    公开(公告)号：US11563024B2

    公开(公告)日：2023-01-24

    申请号：US17002339

    申请日：2020-08-25

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Aaron R. Wilson ,  Paolo Tessariol

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

    Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    14.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20220068952A1

    公开(公告)日：2022-03-03

    申请号：US17002339

    申请日：2020-08-25

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Aaron R. Wilson ,  Paolo Tessariol

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

    Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

    Methods of forming vertically-stacked memory cells
    16.
    发明授权
    Methods of forming vertically-stacked memory cells 有权
    形成垂直堆叠的存储单元的方法

    公开(公告)号：US09136278B2

    公开(公告)日：2015-09-15

    申请号：US14083056

    申请日：2013-11-18

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

    IPC: H01L27/115 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3205 ,  H01L27/108

    CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4966

    Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

    Abstract translation: 一些实施例包括制造集成结构的方法。 在交替的第一和第二水平的叠层上形成含金属的材料。 通过含金属材料和叠层形成开口。 在开口的侧壁处沿着堆叠形成重叠的垂直堆叠的电部件。 一些实施例包括形成垂直堆叠的存储单元的方法。 含金属的材料形成在交替的二氧化硅水平和导电掺杂的硅层上。 通过含金属材料和叠层形成第一开口。 腔体形成为延伸到沿着第一开口的侧壁的导电掺杂的硅层中。 电荷阻挡电介质和电荷存储结构形成在空腔内以留下第二开口。 第二开口的侧壁衬有栅极电介质，然后在第二开口内形成通道材料。

    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING RECESSES
    18.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING RECESSES 有权
    形成具有凹凸的半导体器件的方法

    公开(公告)号：US20130309839A1

    公开(公告)日：2013-11-21

    申请号：US13951793

    申请日：2013-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

    Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

    Abstract translation: Fin-FET（鳍场效应晶体管）器件和制造方法被公开。 鳍式FET器件包括可在源极区域和漏极区域之间形成沟道区域的双鳍结构。 在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在一对STI结构之间限定衬底的一部分中的凹部，以及凹陷 所述一对STI结构使得所得到的双翅片结构从所述基板的有效表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

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