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    Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
    2.
    发明授权
    Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells 有权
    制造集成结构的方法，以及形成垂直堆叠的存储单元的方法

    公开(公告)号：US09305938B2

    公开(公告)日：2016-04-05

    申请号：US14824942

    申请日：2015-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

    IPC: H01L27/115 ,  H01L27/108

    CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4966

    Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

    Abstract translation: 一些实施例包括制造集成结构的方法。 在交替的第一和第二水平的叠层上形成含金属的材料。 通过含金属材料和叠层形成开口。 在开口的侧壁处沿着堆叠形成重叠的垂直堆叠的电部件。 一些实施例包括形成垂直堆叠的存储单元的方法。 含金属的材料形成在交替的二氧化硅水平和导电掺杂的硅层上。 通过含金属材料和叠层形成第一开口。 腔体形成为延伸到沿着第一开口的侧壁的导电掺杂的硅层中。 电荷阻挡电介质和电荷存储结构形成在空腔内以留下第二开口。 第二开口的侧壁衬有栅极电介质，然后在第二开口内形成通道材料。

    Chemistry and Compositions for Manufacturing Integrated Circuits
    3.
    发明申请
    Chemistry and Compositions for Manufacturing Integrated Circuits 审中-公开
    制造集成电路的化学和组成

    公开(公告)号：US20140264152A1

    公开(公告)日：2014-09-18

    申请号：US14290832

    申请日：2014-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Aaron R. Wilson ,  Mark Kiehlbauch

    IPC: C09K13/00

    CPC classification number: C09K13/00 ,  H01L21/31122

    Abstract: In the manufacture of integrated circuits, reactive compositions that include a reactive etchant species and an oxygen-containing species can provide selective removal of target material and can reduce contamination of gas delivery lines.

    Abstract translation: 在集成电路的制造中，包括反应性蚀刻剂物质和含氧物质的反应性组合物可以提供目标材料的选择性去除并且可以减少气体输送管线的污染。

    USING POSITIVE DC OFFSET OF BIAS RF TO NEUTRALIZE CHARGE BUILD-UP OF ETCH FEATURES
    4.
    发明申请
    USING POSITIVE DC OFFSET OF BIAS RF TO NEUTRALIZE CHARGE BUILD-UP OF ETCH FEATURES 审中-公开
    使用偏置RF的积极直流偏移来中和特征的充电建立

    公开(公告)号：US20130220549A1

    公开(公告)日：2013-08-29

    申请号：US13855340

    申请日：2013-04-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron R. Wilson

    IPC: H01L21/3065

    CPC classification number: H01L21/3065 ,  H01J37/32706 ,  H01L21/6833 ,  H02N13/00

    Abstract: Apparatus, systems and methods for plasma etching substrates are provided that achieve dissipation of charge build-up on a substrate being plasma etched to avoid notching or twisting in high aspect ratio contents and similar features. Charge build-up on a substrate being etched by plasma etching can be dissipated by a method for etching a substrate, the method comprising: providing a plasma processing chamber comprising a chamber enclosure and a substrate support adapted to support a substrate within the chamber enclosure; supporting a substrate on the substrate support; forming a plasma within the chamber enclosure such that a surface of the substrate is in contact with the plasma; etching the substrate by generating a negative bias on the substrate surface relative to the plasma; and intermittently changing the bias on the substrate surface to positive relative to the plasma. The present method can be integrated into known plasma processing systems.

    Abstract translation: 提供了用于等离子体蚀刻衬底的装置，系统和方法，其实现在等离子体蚀刻的衬底上的电荷积聚的消散，以避免在高纵横比内容和类似特征中的开槽或扭曲。 通过等离子体蚀刻蚀刻的衬底上的电荷积聚可以通过用于蚀刻衬底的方法来消散，该方法包括：提供等离子体处理室，其包括适于支撑腔室外壳内的衬底的腔室封壳和衬底支撑件; 支撑衬底支撑上的衬底; 在所述室外壳内形成等离子体，使得所述基板的表面与所述等离子体接触; 通过在衬底表面上相对于等离子体产生负偏压来蚀刻衬底; 并且间歇性地将衬底表面上的偏压相对于等离子体改变为正。 本方法可以集成到已知的等离子体处理系统中。

    Methods of forming semiconductor devices having recesses
    6.
    发明授权
    Methods of forming semiconductor devices having recesses 有权
    形成具有凹槽的半导体器件的方法

    公开(公告)号：US09219001B2

    公开(公告)日：2015-12-22

    申请号：US13951793

    申请日：2013-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

    IPC: H01L21/336 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

    Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

    Abstract translation: Fin-FET（鳍场效应晶体管）器件和制造方法被公开。 鳍式FET器件包括可在源极区域和漏极区域之间形成沟道区域的双鳍结构。 在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在一对STI结构之间限定衬底的一部分中的凹部，以及凹陷 所述一对STI结构使得所得到的双翅片结构从所述基板的有效表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

    Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells
    7.
    发明申请
    Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells 有权
    制造集成结构的方法，以及形成垂直堆积记忆细胞的方法

    公开(公告)号：US20150348991A1

    公开(公告)日：2015-12-03

    申请号：US14824942

    申请日：2015-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4966

    Abstract: Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.

    Abstract translation: 一些实施例包括制造集成结构的方法。 在交替的第一和第二水平的叠层上形成含金属的材料。 通过含金属材料和叠层形成开口。 在开口的侧壁处沿着堆叠形成重叠的垂直堆叠的电部件。 一些实施例包括形成垂直堆叠的存储单元的方法。 含金属的材料形成在交替的二氧化硅水平和导电掺杂的硅层上。 通过含金属材料和叠层形成第一开口。 腔体形成为延伸到沿着第一开口的侧壁的导电掺杂的硅层中。 电荷阻挡电介质和电荷存储结构形成在空腔内以留下第二开口。 第二开口的侧壁衬有栅极电介质，然后在第二开口内形成通道材料。

    Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells
    9.
    发明申请
    Methods of Fabricating Integrated Structures, and Methods of Forming Vertically-Stacked Memory Cells 有权
    制造集成结构的方法，以及形成垂直堆积记忆细胞的方法

    公开(公告)号：US20140273462A1

    公开(公告)日：2014-09-18

    申请号：US13835551

    申请日：2013-03-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fatma Arzum Simsek-Ege ,  Aaron R. Wilson

    IPC: H01L27/115

    CPC classification number: H01L27/11578 ,  H01L21/0334 ,  H01L21/0335 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31144 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

    Abstract: Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.

    Abstract translation: 一些实施例包括形成垂直堆叠的存储器单元的方法。 形成开口部分地延伸通过交替的电绝缘水平和导电水平的堆叠。 沿着开口的侧壁形成衬垫，然后蚀刻叠层以延伸开口。 在蚀刻期间衬垫至少部分消耗，并形成钝化材料。 在蚀刻期间发生三个区域，其中一个区域是由衬垫保护的开口的上部区域，另一个区域是由钝化材料而不是衬垫保护的开口的中间区域，另一个区域是 开口的下部区域不被钝化材料或衬垫保护。 腔体形成为延伸到沿开口侧壁的导电水平。 电荷阻挡电介质和电荷存储结构形成在空腔内。

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    10.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20230118763A1

    公开(公告)日：2023-04-20

    申请号：US18083420

    申请日：2022-12-16

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Aaron R. Wilson ,  Paolo Tessariol

    IPC: H10B43/27 ,  H10B41/10 ,  H10B43/35 ,  H10B41/27 ,  H10B43/10 ,  H10B41/35

    Abstract: Some embodiments include an integrated assembly having a first deck with first memory cells arranged in first tiers disposed one atop another, and having a second deck over the first deck and with second memory cells arranged in second tiers disposed one atop another. Cell-material-pillars pass through the first and second decks. The cell-material-pillars have first inter-deck inflections associated with a boundary between the first and second decks. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. A panel is between the first and second memory-block-regions. The panel has a second inter-deck inflection associated with the boundary between the first and second decks. Some embodiments include methods of forming integrated assemblies.

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