公开(公告)号：US20140036584A1

公开(公告)日：2014-02-06

申请号：US14050500

申请日：2013-10-10

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra V. Mouli

IPC: G11C11/409

CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract translation: 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US20210375925A1

公开(公告)日：2021-12-02

申请号：US17445157

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US20190067326A1

公开(公告)日：2019-02-28

申请号：US16111357

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L29/22 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US09293185B2

公开(公告)日：2016-03-22

申请号：US14246896

申请日：2014-04-07

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra V. Mouli

IPC: G11C11/24 ,  G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  G11C11/409 ,  H01L27/07

CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract translation: 无电容器的存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成无电容器的存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US20150035082A1

公开(公告)日：2015-02-05

申请号：US14518567

申请日：2014-10-20

Applicant: Micron Technology, Inc.

Inventor： Chandra V. Mouli

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/326

CPC classification number: H01L29/1041 ,  H01L21/326 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785

Abstract: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.

Abstract translation: 半导体器件结构包括在其晶体管沟道下方具有能量势垒的晶体管。 能量屏障防止存储的电荷从晶体管沟道泄漏到大块衬底中。 还公开了制造包括能量屏障的半导体器件的方法。

公开(公告)号：US20140252449A1

公开(公告)日：2014-09-11

申请号：US14223410

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra V. Mouli ,  Di Li

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Abstract translation: 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

公开(公告)号：US20140219017A1

公开(公告)日：2014-08-07

申请号：US14246896

申请日：2014-04-07

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra V. Mouli

IPC: G11C11/401 ,  H01L29/66

CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract translation: 无电容器存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成无电容器存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US08724372B2

公开(公告)日：2014-05-13

申请号：US14050500

申请日：2013-10-10

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra V. Mouli

IPC: G11C11/24

CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Abstract translation: 无电容器存储单元，存储器件，系统和形成无电容器的存储单元的工艺包括在体半导体衬底的基本上物理隔离的部分的有源区中形成无电容器存储单元。 在有源区上形成传输晶体管，用于与字线耦合。 无电容器存储单元还包括沿着有效区域的至少一个垂直侧垂直配置的读/写使能晶体管，并且在逻辑状态的读取期间可操作，逻辑状态被存储为电荷的浮动体区域 有效区域，导致传输晶体管的不同可确定的阈值电压。

公开(公告)号：US08582350B2

公开(公告)日：2013-11-12

申请号：US13902498

申请日：2013-05-24

Applicant: Micron Technology, Inc.

Inventor： Fernando Gonzalez ,  Chandra V. Mouli

IPC: G11C11/24

CPC classification number: G11C11/401 ,  G11C11/405 ,  G11C11/408 ,  G11C11/409 ,  H01L27/0705 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7841

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

公开(公告)号：US11769795B2

公开(公告)日：2023-09-26

申请号：US17499410

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L21/762 ,  H10B12/00

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H10B12/053 ,  H10B12/31 ,  H10B12/34

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.