公开(公告)号：US11067628B2

公开(公告)日：2021-07-20

申请号：US16577267

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Chikara Kondo ,  Ryo Fujimaki

IPC: G01R31/00 ,  G01R31/3177 ,  G11C29/12 ,  H01L25/18 ,  G11C11/4093

Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

公开(公告)号：US20210088583A1

公开(公告)日：2021-03-25

申请号：US16577267

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Chikara Kondo ,  Ryo Fujimaki

IPC: G01R31/3177 ,  G11C11/4093 ,  H01L25/18 ,  G11C29/12

Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

公开(公告)号：US10943625B2

公开(公告)日：2021-03-09

申请号：US16721515

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C7/10 ,  G11C19/28 ,  G11C7/22 ,  G11C16/32

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US10790039B1

公开(公告)日：2020-09-29

申请号：US16584520

申请日：2019-09-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyunui Lee ,  Chiaki Dono

IPC: G11C29/02 ,  G11C29/12 ,  G11C29/48 ,  H01L23/48 ,  H01L23/498 ,  H01L27/108 ,  G11C29/30 ,  G11C29/56 ,  G11C29/44

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.

公开(公告)号：US10468114B2

公开(公告)日：2019-11-05

申请号：US16013290

申请日：2018-06-20

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Taihei Shido ,  Yuki Ebihara

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/44 ,  G11C29/12 ,  G11C29/48

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

公开(公告)号：US20190122708A1

公开(公告)日：2019-04-25

申请号：US16225303

申请日：2018-12-19

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

IPC: G11C7/10 ,  G11C7/22 ,  G11C19/28

Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

公开(公告)号：US20180301202A1

公开(公告)日：2018-10-18

申请号：US16013290

申请日：2018-06-20

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Taihei Shido ,  Yuki Ebihara

IPC: G11C29/38 ,  G11C29/00 ,  G11C29/48 ,  G11C29/44 ,  G11C29/36 ,  G11C29/12

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.

公开(公告)号：US10008287B2

公开(公告)日：2018-06-26

申请号：US15217719

申请日：2016-07-22

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Taihei Shido ,  Yuki Ebihara

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/44

Abstract: Apparatuses and methods for an interface chip are described. An example apparatus includes a first chip. The first chip includes, on a single semiconductor substrate, first terminals, circuit groups, and terminal groups corresponding to the circuit groups, each of the circuit groups including circuit blocks. A control circuit in the first chip selects one of the circuit groups and electrically couples the first terminals to the circuit blocks of the selected circuit group. Second terminals are included in each of the terminal groups. A number of all of the second terminals in each of the terminal groups is smaller than a number of all of the circuit blocks in the corresponding circuit group. The first chip further includes, for example, a remapping circuit.

公开(公告)号：US11120849B2

公开(公告)日：2021-09-14

申请号：US16459439

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Chiaki Dono

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22 ,  G06F13/42

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

公开(公告)号：US10854310B2

公开(公告)日：2020-12-01

申请号：US16436767

申请日：2019-06-10

Applicant: Micron Technology, Inc.

Inventor： Chiaki Dono ,  Taihei Shido ,  Yuki Ebihara

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C29/44 ,  G11C29/12 ,  G11C29/48

Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.