公开(公告)号：US20210042219A1

公开(公告)日：2021-02-11

申请号：US17079138

申请日：2020-10-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/02 ,  G06F13/16

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

公开(公告)号：US10713156B2

公开(公告)日：2020-07-14

申请号：US16126405

申请日：2018-09-10

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F1/20 ,  G06F12/02 ,  G06F3/06 ,  G11C7/04 ,  G06F1/3234 ,  G06F12/122 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42 ,  G11C11/406

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

公开(公告)号：US20140304444A1

公开(公告)日：2014-10-09

申请号：US14247833

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F12/02 ,  G06F13/24 ,  G06F12/12

CPC classification number: G06F12/0223 ,  G06F1/206 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/122 ,  G06F13/1668 ,  G06F13/24 ,  G06F13/4282 ,  G06F2212/1016 ,  G11C7/04 ,  G11C11/40626 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/16

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

Abstract translation: 描述了将存储区域映射到基于存储器区域的热数据的处理的方法。 在一些实施例中，存储器控制器可以接收存储器分配请求。 存储器分配请求可以包括逻辑存储器地址。 该方法还可以包括基于存储器系统的存储器区域的热数据将逻辑存储器地址映射到存储器系统的存储器区域中的地址。 还描述了附加的方法和系统。

公开(公告)号：US20250077411A1

公开(公告)日：2025-03-06

申请号：US18954112

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： David A. Roberts

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16

Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.

公开(公告)号：US12158840B2

公开(公告)日：2024-12-03

申请号：US18512850

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： David A. Roberts

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16

Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.

公开(公告)号：US20240086315A1

公开(公告)日：2024-03-14

申请号：US18512850

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： David A. Roberts

IPC: G06F12/02 ,  G06F12/0882 ,  G06F13/16

CPC classification number: G06F12/0238 ,  G06F12/0292 ,  G06F12/0882 ,  G06F13/1621 ,  G06F13/1689

Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.

公开(公告)号：US11860773B2

公开(公告)日：2024-01-02

申请号：US17591729

申请日：2022-02-03

Applicant: Micron Technology, Inc.

Inventor： David A. Roberts

IPC: G06F12/02 ,  G06F13/16 ,  G06F12/0882

CPC classification number: G06F12/0238 ,  G06F12/0292 ,  G06F12/0882 ,  G06F13/1621 ,  G06F13/1689

Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.

公开(公告)号：US11625321B2

公开(公告)日：2023-04-11

申请号：US17079138

申请日：2020-10-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/02 ,  G06F13/16

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

公开(公告)号：US20220199144A1

公开(公告)日：2022-06-23

申请号：US17591319

申请日：2022-02-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts

IPC: G11C11/4078

Abstract: Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

公开(公告)号：US11810612B2

公开(公告)日：2023-11-07

申请号：US17591319

申请日：2022-02-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David A. Roberts

IPC: G11C11/4078

CPC classification number: G11C11/4078

Abstract: Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.