公开(公告)号：US10656995B2

公开(公告)日：2020-05-19

申请号：US16150501

申请日：2018-10-03

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Fulvio Rori

IPC: G11C16/04 ,  G06F11/10 ,  G11C16/10 ,  G06F12/02 ,  G11C29/52 ,  G11C29/42

Abstract: Devices and techniques for performing copy-back operations in a memory device are disclosed herein. A trigger to perform a copy-back operation in relation to a section of data stored on the memory device can be detected. Circuitry of the memory device can then read the section of data at two voltage levels within a read window to obtain a first set of bits and a second set of bits respectively. The first and second sets of bits—which should be the same under normal circumstances—are compared to determine whether a difference between the sets of bits is beyond a threshold. If the difference is beyond a threshold, error correction is invoked prior to completion of the copy-back operation.

公开(公告)号：US20240303187A1

公开(公告)日：2024-09-12

申请号：US18591368

申请日：2024-02-29

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Ryan Hrinya ,  Fulvio Rori ,  Scott A. Stoller ,  Tyler Betz

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Apparatuses and methods for determining performing read operations on a partially programmed block are provided. One example apparatus can include a controller configured to apply a read voltage to a word line in an array of memory cells during a read operation on the word line, apply a first pass voltage to a number of programmed word lines in the array of memory cells during the read operation, and apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells during the read operation.

公开(公告)号：US12086427B2

公开(公告)日：2024-09-10

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F1/28 ,  G06F1/08 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US20240249789A1

公开(公告)日：2024-07-25

申请号：US18417517

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Tarun Singh Yadav ,  Scott Anthony Stoller ,  Pitamber Shukla ,  Fulvio Rori ,  Attila A. Herrera ,  Justin Bates

IPC: G11C29/12

CPC classification number: G11C29/1201 ,  G11C2029/1202

Abstract: Aspects of the present disclosure configure a memory sub-system controller to adaptively allocate word lines (WLs). The controller accesses reliability data of a set of main WLs of a block of the set of memory components. The controller determines that one or more WLs of the set of main WLs of the block are associated with respective reliability data that transgress a threshold and, in response to determining that the one or more WLs are associated with the respective reliability data that transgress the threshold, replaces the one or more WLs of the set of main WLs of the block with one or more dummy WLs. The controller programs data into the block using the one or more dummy WLs instead of the one or more WLs of the set of main WLs of the block.

公开(公告)号：US20240053894A1

公开(公告)日：2024-02-15

申请号：US17884429

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Giuseppe Cariello ,  Fulvio Rori

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0679 ,  G06F3/0659

Abstract: Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

公开(公告)号：US20220277796A1

公开(公告)日：2022-09-01

申请号：US17747516

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Shannon Marissa Hansen ,  Fulvio Rori ,  Andrea D'Alessandro ,  Jason Lee Nevill ,  Chiara Cerafogli

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

公开(公告)号：US11355200B2

公开(公告)日：2022-06-07

申请号：US16996363

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Shannon Marissa Hansen ,  Fulvio Rori ,  Andrea D'Alessandro ,  Jason Lee Nevill ,  Chiara Cerafogli

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11556

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

公开(公告)号：US11200925B2

公开(公告)日：2021-12-14

申请号：US16946305

申请日：2020-06-16

Applicant: Micron Technology, Inc.

Inventor： Jonathan Wen Jian Oh ,  Aaron James Olson ,  Fulvio Rori ,  Qisong Lin ,  Preston A. Thomson

IPC: G11C7/10 ,  G06F12/0882 ,  G06F9/30 ,  G06F11/27

Abstract: A programmable memory device includes a read only memory (ROM) block to store instructions associated with functionality of the programmable memory device. The device includes a memory array having a set of reserved pages to store updates to be performed on the ROM block. The device includes a controller coupled to the ROM block and the memory array. The controller is to execute the instructions to: execute a set features command; program, in execution of the set features command, a set of sub-feature parameters to a specified feature address of the set of reserved pages, wherein the set of sub-feature parameters are to trigger operation within a ROM-emulated memory (REM) profile mode; and program a REM-profiled page of the set of reserved pages with REM data received from a host system.

公开(公告)号：US20210342100A1

公开(公告)日：2021-11-04

申请号：US17373301

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Fulvio Rori ,  Jonathan W. Oh ,  Giuseppe Cariello

IPC: G06F3/06 ,  G11C16/10 ,  G06F11/10 ,  G11C16/26 ,  G11C16/04 ,  G11C29/52

Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

公开(公告)号：US20210303172A1

公开(公告)日：2021-09-30

申请号：US17346136

申请日：2021-06-11

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Fulvio Rori ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.