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    VERTICALLY STACKED STORAGE NODES AND ACCESS DEVICES WITH VERTICAL ACCESS LINES
    11.
    发明公开
    VERTICALLY STACKED STORAGE NODES AND ACCESS DEVICES WITH VERTICAL ACCESS LINES 审中-公开

    公开(公告)号：US20240064956A1

    公开(公告)日：2024-02-22

    申请号：US17891839

    申请日：2022-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/10873

    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and horizontally oriented storage nodes that are vertically separated from the access devices. Vertically oriented gates are separated from the respective channel regions by gate dielectrics, and horizontally oriented digit lines are coupled to respective first source/drain regions. The horizontally oriented storage nodes each have a first electrode coupled to the second source/drain regions of the access devices and each first electrode opposes two different sides of the horizontal access devices including an electrical contact with a vertical side of the second source/drain regions.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    16.
    发明公开
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 审中-公开

    公开(公告)号：US20230298652A1

    公开(公告)日：2023-09-21

    申请号：US18200871

    申请日：2023-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    CPC classification number: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND CONDUCTIVE SHIELD STRUCTURE
    17.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND CONDUCTIVE SHIELD STRUCTURE 有权

    公开(公告)号：US20230138322A1

    公开(公告)日：2023-05-04

    申请号：US17515065

    申请日：2021-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Richard E. Fackenthal ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11575 ,  H01L29/10 ,  H01L21/28

    Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.

    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
    19.
    发明申请
    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors 有权

    公开(公告)号：US20230014320A1

    公开(公告)日：2023-01-19

    申请号：US17947401

    申请日：2022-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

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