公开(公告)号：US20220293506A1

公开(公告)日：2022-09-15

申请号：US17830022

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

公开(公告)号：US11309285B2

公开(公告)日：2022-04-19

申请号：US16440328

申请日：2019-06-13

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00

Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

公开(公告)号：US20220084977A1

公开(公告)日：2022-03-17

申请号：US17023143

申请日：2020-09-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Madison E. Wale ,  James L. Voelz ,  Dylan W. Southern

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/13 ,  H01L25/065 ,  H01L25/00

Abstract: Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.

公开(公告)号：US11196142B2

公开(公告)日：2021-12-07

申请号：US16118785

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01Q1/22 ,  H01L23/48 ,  H01L21/02

Abstract: Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

公开(公告)号：US20210233894A1

公开(公告)日：2021-07-29

申请号：US16774900

申请日：2020-01-28

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/532 ,  H01L25/00 ,  H01L21/683 ,  H01L23/528 ,  H01L23/522

Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.

公开(公告)号：US20210134670A1

公开(公告)日：2021-05-06

申请号：US16671577

申请日：2019-11-01

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Owen R. Fay

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L21/463

Abstract: A method of coupling a first semiconductor device to a second semiconductor device can include encapsulating solder balls on a first surface of a first substrate of the first semiconductor device with an encapsulant material. In some embodiments, the method includes removing a portion of the encapsulant material and a portion the solder balls to form a mating surface. The method can include reflowing the solder balls. In some embodiments, the method includes inserting exposed conductive pillars of the second semiconductor device into the reflowed solder balls.

公开(公告)号：US10998271B1

公开(公告)日：2021-05-04

申请号：US16671558

申请日：2019-11-01

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Akshay N. Singh

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

公开(公告)号：US20210118849A1

公开(公告)日：2021-04-22

申请号：US16939650

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Aparna U. Limaye ,  Dong Soon Lim ,  Randon K. Richards ,  Owen R. Fay

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.

公开(公告)号：US10950565B2

公开(公告)日：2021-03-16

申请号：US16810768

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Kyle S. Mayer ,  Owen R. Fay

IPC: H01L23/00 ,  H01L21/288

Abstract: Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

公开(公告)号：US20200258859A1

公开(公告)日：2020-08-13

申请号：US16270112

申请日：2019-02-07

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle ,  John F. Kaeding ,  Owen R. Fay ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L23/00

Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.