公开(公告)号：US11966303B2

公开(公告)日：2024-04-23

申请号：US17877779

申请日：2022-07-29

Applicant: Micron Technology, Inc.

Inventor： Robert Mason ,  Scott A. Stoller ,  Pitamber Shukla ,  Kenneth W. Marr ,  Chi Ming Chu ,  Hossein Afkhami

IPC: G06F11/14 ,  G06F9/30

CPC classification number: G06F11/1471 ,  G06F9/30098 ,  G06F11/1469

Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

公开(公告)号：US20240071440A1

公开(公告)日：2024-02-29

申请号：US17897438

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Robert W. Mason ,  Pitamber Shukla ,  Steven Michael Kientz

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/109 ,  G11C7/222

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.

公开(公告)号：US11847335B2

公开(公告)日：2023-12-19

申请号：US17212437

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Scott Anthony Stoller ,  Niccolo' Righetti ,  Giuseppina Puzzilli

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0679

Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

公开(公告)号：US20230402103A1

公开(公告)日：2023-12-14

申请号：US17887765

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Jiun-horng Lai ,  Pitamber Shukla ,  Ching-Huang Lu ,  Chengkuan Yin ,  Yoshiaki Fukuzumi

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

公开(公告)号：US20230360708A1

公开(公告)日：2023-11-09

申请号：US17739789

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Jiun-Horng Lai ,  Ching-Huang Lu ,  Fulvio Rori ,  Wai Ying Lo ,  Scott A. Stoller

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/3445

Abstract: Memory systems with flexible erase suspend-resume operations are described herein. In one embodiment, a memory device is configured to receive an erase suspend command while a first erase pulse of an erase operation is at a flattop voltage. In response, the memory device suspends the erase operation. The memory device further resumes the erase operation such that a second erase pulse of the erase operation is ramped to the flattop voltage. Absent intervening erase suspend operations, erase operations of the memory device can include a single erase pulse that remains at the flattop voltage for a total duration. A first total duration plus a second total duration the first and second erase pulses, respectively, remain at the flattop voltage remains less than or equal to the total duration the single erase pulse remains at the flattop voltage.

公开(公告)号：US20230214299A1

公开(公告)日：2023-07-06

申请号：US17566921

申请日：2021-12-31

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Vipul Patel ,  Scott A. Stoller

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/0882 ,  G06F3/06

CPC classification number: G06F11/108 ,  G06F11/0772 ,  G06F11/0793 ,  G06F12/0882 ,  G06F3/0656 ,  G06F3/0619 ,  G06F3/0688

Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

公开(公告)号：US20230113480A1

公开(公告)日：2023-04-13

申请号：US18080309

申请日：2022-12-13

Applicant: Micron Technology, Inc.

Inventor： Scott Anthony Stoller ,  Pitamber Shukla ,  Anita Marguerite Ekren

IPC: G06F11/07 ,  G06F11/30

Abstract: A log of error events associated with a memory device is maintained. Each error event included in the log is associated with one of multiple physical locations within the memory device. A physical location within the memory device is identified for background scanning based on the log of error events. A background scan is performed on the physical location identified based on the log of error events.

公开(公告)号：US20220343985A1

公开(公告)日：2022-10-27

申请号：US17238818

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Scott A. Stoller ,  Pitamber Shukla ,  Kishore Kumar Muchherla ,  Fulvio Rori ,  Bin Wang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: Described are systems and methods for providing power loss immunity in memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a programming pulse to be applied to to one or more wordlines of the memory array; responsive to determining that a threshold voltage of one or more memory cells of the memory array has reached a pre-program verify level, causing a first bias voltage level to be applied to a first subset of bitlines of the memory array and causing a second bias voltage level to be applied to a second subset of bitlines of the memory array.

公开(公告)号：US20220197536A1

公开(公告)日：2022-06-23

申请号：US17127373

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

公开(公告)号：US20250022523A1

公开(公告)日：2025-01-16

申请号：US18902035

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Avinash Rajagiri ,  Devin Batutis

IPC: G11C29/02 ,  G06F11/07 ,  G11C29/00 ,  G11C29/04

Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.