公开(公告)号：US20200233741A1

公开(公告)日：2020-07-23

申请号：US16744025

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  Peter Mayer ,  Wolfgang Anton Spirki ,  Thomas Hein ,  Michael Dieter Richter ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F11/10 ,  G06F12/02 ,  G06F11/16

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

公开(公告)号：US09948300B1

公开(公告)日：2018-04-17

申请号：US15464012

申请日：2017-03-20

Applicant: Micron Technology, Inc.

Inventor： Roy E. Greeff

IPC: H03K19/00 ,  H03K5/1534 ,  H03K19/003

CPC classification number: H03K19/0005 ,  H03K5/1534 ,  H03K19/00323 ,  H03K19/018521 ,  H04L25/0286

Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period proceeding the first portion.

公开(公告)号：US20130187679A1

公开(公告)日：2013-07-25

申请号：US13796410

申请日：2013-03-12

Applicant: Micron Technology, Inc.

Inventor： Roy E. Greeff ,  David K. Ovard

IPC: H03K19/003

CPC classification number: H03K19/003 ,  G06F13/4086

Abstract: Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.

公开(公告)号：US12189996B2

公开(公告)日：2025-01-07

申请号：US18490589

申请日：2023-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US11862294B2

公开(公告)日：2024-01-02

申请号：US17936048

申请日：2022-09-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C7/22

CPC classification number: G11C8/18 ,  G11C7/1063 ,  G11C7/222 ,  G11C8/06

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

公开(公告)号：US11809715B2

公开(公告)日：2023-11-07

申请号：US17239460

申请日：2021-04-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  H04L25/49 ,  G06F13/42 ,  G06F13/40 ,  G11C7/10

CPC classification number: G06F3/0613 ,  G06F3/0607 ,  G06F3/0635 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4234 ,  G06F13/4282 ,  G11C7/1072 ,  H04L25/4923

Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

公开(公告)号：US11797229B2

公开(公告)日：2023-10-24

申请号：US17360943

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F1/04 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F13/1689 ,  G06F2213/16

Abstract: A memory subsystem architecture that includes two register clock driver (RCD) devices to increase a number of output drivers for signaling memories of the memory subsystem is described herein. In a two RCD device implementation, first and second RCD devices may contemporaneously provide first subchannel C/A information and second subchannel C/A information, respectively, to respective first and second group of memories of the memory subsystem responsive to a common clock signal. Because each of the first and second RCD devices operate responsive to the common clock signal, operation of the first and second RCD devices may be synchronized such that all subchannel driver circuits drive respective subchannel C/A information contemporaneously.

公开(公告)号：US20220005515A1

公开(公告)日：2022-01-06

申请号：US17360964

申请日：2021-06-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G11C8/18 ,  G11C8/06 ,  G11C7/10 ,  G11C7/22

Abstract: A memory subsystem architecture that includes clock signal routing architecture to split a clock signal to support two register clock driver (RCD) devices. The clock signal routing architecture may include clock signal splitter circuit that enables contemporaneous provision of a common clock signal to the two register clock driver devices. The clock signal splitter circuit may have three legs: a first leg to receive the clock signal from an external bus, and two similar legs to route the clock signal to the RCD devices.

公开(公告)号：US11106367B2

公开(公告)日：2021-08-31

申请号：US16507292

申请日：2019-07-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy Hollis ,  Roy E. Greeff

IPC: G06F3/06 ,  G06F13/40 ,  G11C7/10 ,  G06F13/42 ,  H04L25/49

Abstract: Apparatuses and methods for multi-level communication architectures are disclosed herein. An example apparatus may include a driver circuit configured to convert a plurality of bitstreams into a plurality of multilevel signals. A count of the plurality of bitstreams is greater than count of the plurality of multilevel signals. The driver circuit further configured to drive the plurality of multilevel signals onto a plurality of signal lines using individual drivers. A driver of the individual drivers is configured to drive more than two voltages.

公开(公告)号：US10128843B2

公开(公告)日：2018-11-13

申请号：US15941964

申请日：2018-03-30

Applicant: Micron Technology, Inc.

Inventor： Roy E. Greeff

IPC: H03K19/00 ,  H03K5/1534 ,  H03K19/003

Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.