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    SENSE OPERATION FLAGS IN A MEMORY DEVICE
    13.
    发明申请
    SENSE OPERATION FLAGS IN A MEMORY DEVICE 有权
    在存储器中识别操作标志

    公开(公告)号：US20150363313A1

    公开(公告)日：2015-12-17

    申请号：US14833175

    申请日：2015-08-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F12/08 ,  G06F13/28 ,  G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

    Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

    Sense flags in a memory device
    15.
    发明授权
    Sense flags in a memory device 有权

    公开(公告)号：US10409506B2

    公开(公告)日：2019-09-10

    申请号：US16117348

    申请日：2018-08-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F3/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

    Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

    Sense flags in a memory device
    19.
    发明授权
    Sense flags in a memory device 有权

    公开(公告)号：US11029861B2

    公开(公告)日：2021-06-08

    申请号：US16543743

    申请日：2019-08-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F3/06 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.

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