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    SEMICONDUCTOR DEVICES WITH DUPLICATED DIE BOND PADS AND ASSOCIATED DEVICE PACKAGES AND METHODS OF MANUFACTURE
    12.
    发明申请
    SEMICONDUCTOR DEVICES WITH DUPLICATED DIE BOND PADS AND ASSOCIATED DEVICE PACKAGES AND METHODS OF MANUFACTURE 审中-公开

    公开(公告)号：US20190319013A1

    公开(公告)日：2019-10-17

    申请号：US16455590

    申请日：2019-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Nathan J. Sirocka ,  Trismardawi Tanadi ,  Andrew D. Proescholdt

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.

    WORDLINE LEAKAGE TEST MANAGEMENT
    15.
    发明公开
    WORDLINE LEAKAGE TEST MANAGEMENT 审中-公开

    公开(公告)号：US20240036753A1

    公开(公告)日：2024-02-01

    申请号：US17877240

    申请日：2022-07-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Wai Leong Chin ,  Francis Chee Khai Chew ,  Trismardawi Tanadi ,  Chun Sum Yeung ,  Lawrence Dumalag ,  Ekamdeep Singh

    IPC: G06F3/06

    CPC classification number: G06F3/064 ,  G06F3/0653 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. In response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. A result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.

    Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
    16.
    发明授权
    Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture 有权

    公开(公告)号：US10388630B2

    公开(公告)日：2019-08-20

    申请号：US15829428

    申请日：2017-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Nathan J. Sirocka ,  Trismardawi Tanadi ,  Andrew D. Proescholdt

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.

    APPARATUSES AND RELATED METHODS FOR STAGGERING POWER-UP OF A STACK OF SEMICONDUCTOR DIES
    19.
    发明申请
    APPARATUSES AND RELATED METHODS FOR STAGGERING POWER-UP OF A STACK OF SEMICONDUCTOR DIES 有权
    用于分层半导体芯片堆叠的装置及相关方法

    公开(公告)号：US20150070056A1

    公开(公告)日：2015-03-12

    申请号：US14020549

    申请日：2013-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Trismardawi Tanadi

    IPC: G05F1/66 ,  H01L25/11

    CPC classification number: G05F1/66 ,  G06F1/26 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L2924/0002 ,  H03K5/14 ,  H03K17/223 ,  H03K2005/00234 ,  H01L2924/00

    Abstract: An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

    Abstract translation: 一种包括堆叠中的半导体管芯的设备。 半导体管芯被配置为以交错方式上电。 为电子设备供电的方法包括：利用堆叠中的半导体管芯检测上电事件，并且响应于上电事件，在第一时间对堆叠中的第一半导体管芯供电，并且为第二个电源加电 半导体芯片在第二时间处于与第一次不同的第二时间。

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